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* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-2/+4
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM: rename addrmode7 to addr_offset_none.Jim Grosbach2011-08-021-1/+1
| | | | | | Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-271-0/+1
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-1/+2
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* ARM parsing and encoding for SVC instruction.Jim Grosbach2011-07-261-0/+1
| | | | llvm-svn: 136090
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-251-0/+1
| | | | llvm-svn: 136006
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-221-1/+1
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-4/+6
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-211-1/+2
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-201-0/+2
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* ARM assembly parsing for MOV (immediate).Jim Grosbach2011-07-191-0/+1
| | | | | | | | Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-131-0/+2
| | | | llvm-svn: 135092
* Give the ARM BKPT instruction the right operand type.Jim Grosbach2011-07-131-0/+1
| | | | | | The immediate is of limited range and the operand type should reflect that. llvm-svn: 135066
* Resynchronize EDInfo.h and EDEmitter.cpp.Shantonu Sen2011-07-111-14/+13
| | | | | | | | | | | | The enum names as well as order (i.e. value) had skewed, which means that consumers of the tablegen-ed table would see different values than intended. Make both files have a superset of enums, and add classification as needed for numMCOperands. Reviewed by Owen Anderson llvm-svn: 134905
* Don't require pseudo-instructions to carry encoding information.Jim Grosbach2011-07-061-0/+5
| | | | | | | | | | For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. llvm-svn: 134539
* ARM Assembly support for Thumb mov-immediate.Jim Grosbach2011-06-271-0/+1
| | | | | | | | | | | Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. llvm-svn: 133966
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-311-0/+1
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
* Fixed MC encoding for index_align for VLD1/VST1 (single element from one ↵Mon P Wang2011-05-091-0/+1
| | | | | | lane) for size 32 llvm-svn: 131085
* Remove unused STL header includes.Jay Foad2011-04-231-1/+0
| | | | llvm-svn: 130068
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+4
| | | | llvm-svn: 128236
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-181-0/+1
| | | | llvm-svn: 127888
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-071-3/+4
| | | | | | | | expand the testing of the narrowing shift right instructions. No functionality change. llvm-svn: 127193
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+3
| | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> llvm-svn: 126723
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-0/+2
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-041-0/+7
| | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
* TableGen: PointerLikeRegClass can be accepted to operand.NAKAMURA Takumi2011-01-261-1/+2
| | | | llvm-svn: 124271
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+2
| | | | | | instruction llvm-svn: 123770
* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-131-0/+2
| | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-131-1/+1
| | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-0/+1
| | | | llvm-svn: 121798
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-6/+8
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-141-0/+1
| | | | | | | | much later, which makes the entire process cleaner. llvm-svn: 121735
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-1/+0
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-0/+1
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-131-0/+2
| | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. llvm-svn: 121710
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-1/+1
| | | | llvm-svn: 121659
* Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach2010-12-101-0/+1
| | | | llvm-svn: 121496
* Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach2010-12-101-0/+1
| | | | llvm-svn: 121493
* Thumb needs a few different encoding schemes for branch targets. RenameJim Grosbach2010-12-091-1/+1
| | | | | | t_brtarget to be more specific. llvm-svn: 121398
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-091-0/+1
| | | | | | | | | | particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. llvm-svn: 121336
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-081-1/+2
| | | | llvm-svn: 121308
* Add support for loading from a constant pool.Bill Wendling2010-12-081-0/+2
| | | | llvm-svn: 121226
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-061-0/+1
| | | | llvm-svn: 121072
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-011-0/+1
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-301-2/+0
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-301-0/+2
| | | | llvm-svn: 120449
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-301-0/+1
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-181-0/+1
| | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-171-0/+4
| | | | | | | | | instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
* ARM fixup encoding for direct call instructions (BL).Jim Grosbach2010-11-111-0/+2
| | | | llvm-svn: 118829
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