summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/EDEmitter.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-2/+2
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-9/+7
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-271-0/+1
| | | | | | | complex load / store addressing mode) when they have higher cost and when they have more than one use. llvm-svn: 117509
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-271-0/+1
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+4
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+1
| | | | llvm-svn: 116588
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-0/+1
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+2
| | | | llvm-svn: 116421
* Fix spelling error.Cameron Esfahani2010-10-121-2/+2
| | | | llvm-svn: 116282
* trailing whitespaceJim Grosbach2010-10-051-95/+95
| | | | llvm-svn: 115664
* fix bugs in push/pop segment support, rdar://8407242Chris Lattner2010-09-081-4/+12
| | | | llvm-svn: 113422
* remove dead code.Chris Lattner2010-09-011-37/+0
| | | | llvm-svn: 112707
* Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson2010-08-161-1/+1
| | | | | | instructions besides saturate instructions. No functional changes. llvm-svn: 111168
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-0/+1
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-0/+1
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | have 4 bits per register in the operand encoding), but have undefined behavior when the operand value is 13 or 15 (SP and PC, respectively). The trivial coalescer in linear scan sometimes will merge a copy from SP into a subsequent instruction which uses the copy, and if that instruction cannot legally reference SP, we get bad code such as: mls r0,r9,r0,sp instead of: mov r2, sp mls r0, r9, r0, r2 This patch adds a new register class for use by Thumb2 that excludes the problematic registers (SP and PC) and is used instead of GPR for those operands which cannot legally reference PC or SP. The trivial coalescer explicitly requires that the register class of the destination for the COPY instruction contain the source register for the COPY to be considered for coalescing. This prevents errant instructions like that above. PR7499 llvm-svn: 109842
* remove option from tablegen for building static header.Chris Lattner2010-07-201-18/+0
| | | | llvm-svn: 108893
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-0/+1
| | | | llvm-svn: 108769
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-0/+2
| | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-0/+1
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* Add support for the x86 instructions "pusha" and "popa".Nico Weber2010-06-231-0/+4
| | | | llvm-svn: 106671
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-0/+1
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-4/+1
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-0/+1
| | | | llvm-svn: 103760
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+1
| | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng2010-05-061-2/+3
| | | | | | coalescer bug that's fixed by 103170. llvm-svn: 103172
* Fixes to edis that mark x86 call targets asSean Callanan2010-04-231-2/+2
| | | | | | memory operands rather than immediate operands. llvm-svn: 102217
* EDis: Don't include inttypes.h. We support compilers which don't provide it. ↵Benjamin Kramer2010-04-141-2/+0
| | | | | | It was unused anyways. llvm-svn: 101241
* Fixed a nasty layering violation in the edis sourceSean Callanan2010-04-131-51/+53
| | | | | | | | | | | | | | | code. It used to #include the enhanced disassembly information for the targets it supported straight out of lib/Target/{X86,ARM,...} but now it uses a new interface provided by MCDisassembler, and (so far) implemented by X86 and ARM. Also removed hacky #define-controlled initialization of targets in edis. If clients only want edis to initialize a limited set of targets, they can set --enable-targets on the configure command line. llvm-svn: 101179
* Use errs instead of fprintf.Benjamin Kramer2010-04-081-5/+4
| | | | llvm-svn: 100754
* Added support for ARM disassembly to edis.Sean Callanan2010-04-081-169/+410
| | | | | | | | | | | I also added a rule to the ARM target's Makefile to build the ARM-specific instruction information table for the enhanced disassembler. I will add the test harness for all this stuff in a separate commit. llvm-svn: 100735
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-2/+2
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* Check in tablegen changes to fix disassembler related failures caused by r98465.Evan Cheng2010-03-141-0/+4
| | | | llvm-svn: 98468
* Updated the enhanced disassembly library's TableGenSean Callanan2010-02-101-8/+1
| | | | | | | backend to not use exceptions at all except in cases of actual error. llvm-svn: 95762
* Updated the TableGen emitter for the EnhancedSean Callanan2010-02-101-209/+24
| | | | | | | Disassembler to take advantage of the refactored AsmWriterInst.h. Note removed parser code. llvm-svn: 95760
* Fixed some indentation in the AsmWriterInstSean Callanan2010-02-091-0/+1
| | | | | | | | implementation. Also changed the constructor so that it does not require a Record, making it usable by the EDEmitter. llvm-svn: 95715
* Quick fix to make the header file for the enhancedSean Callanan2010-01-291-3/+3
| | | | | | | disassembly information have a better comment (and better guard macros). llvm-svn: 94781
* Added a custom TableGen backend to support theSean Callanan2010-01-291-0/+856
enhanced disassembler, and the necessary makefile rules to build the table for X86. llvm-svn: 94764
OpenPOWER on IntegriCloud