| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | TableGen: PointerLikeRegClass can be accepted to operand. | NAKAMURA Takumi | 2011-01-26 | 1 | -1/+2 |
| * | Add support for parsing and encoding ARM's official syntax for the BFI instru... | Bruno Cardoso Lopes | 2011-01-18 | 1 | -0/+2 |
| * | Add support to the ARM MC infrastructure to support mcr and friends. This req... | Owen Anderson | 2011-01-13 | 1 | -0/+2 |
| * | Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step | Evan Cheng | 2011-01-13 | 1 | -1/+1 |
| * | Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 | Jim Grosbach | 2010-12-14 | 1 | -0/+1 |
| * | The tLDR et al instructions were emitting either a reg/reg or reg/imm | Bill Wendling | 2010-12-14 | 1 | -6/+8 |
| * | Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ... | Owen Anderson | 2010-12-14 | 1 | -0/+1 |
| * | Revert r121721, which broke buildbots. | Owen Anderson | 2010-12-13 | 1 | -1/+0 |
| * | Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provid... | Owen Anderson | 2010-12-13 | 1 | -0/+1 |
| * | In Thumb2, direct branches can be encoded as either a "short" conditional bra... | Owen Anderson | 2010-12-13 | 1 | -0/+2 |
| * | eliminate the Records global variable, patch by Garrison Venn! | Chris Lattner | 2010-12-13 | 1 | -1/+1 |
| * | Thumb unconditional branch binary encoding. rdar://8754994 | Jim Grosbach | 2010-12-10 | 1 | -0/+1 |
| * | Thumb conditional branch binary encodings. rdar://8745367 | Jim Grosbach | 2010-12-10 | 1 | -0/+1 |
| * | Thumb needs a few different encoding schemes for branch targets. Rename | Jim Grosbach | 2010-12-09 | 1 | -1/+1 |
| * | The BLX instruction is encoded differently than the BL, because why not? In | Bill Wendling | 2010-12-09 | 1 | -0/+1 |
| * | Support the "target" encodings for the CB[N]Z instructions. | Bill Wendling | 2010-12-08 | 1 | -1/+2 |
| * | Add support for loading from a constant pool. | Bill Wendling | 2010-12-08 | 1 | -0/+2 |
| * | Add fixup for Thumb1 BL/BLX instructions. | Jim Grosbach | 2010-12-06 | 1 | -0/+1 |
| * | Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR | Jim Grosbach | 2010-12-01 | 1 | -0/+1 |
| * | Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ... | Owen Anderson | 2010-11-30 | 1 | -2/+0 |
| * | Add encoding support for Thumb2 PLD and PLI instructions. | Owen Anderson | 2010-11-30 | 1 | -0/+2 |
| * | Fix the encoding of VLD4-dup alignment. | Bob Wilson | 2010-11-30 | 1 | -0/+1 |
| * | Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ... | Jason W Kim | 2010-11-18 | 1 | -0/+1 |
| * | Proper encoding for VLDM and VSTM instructions. The register lists for these | Bill Wendling | 2010-11-17 | 1 | -0/+4 |
| * | ARM fixup encoding for direct call instructions (BL). | Jim Grosbach | 2010-11-11 | 1 | -0/+2 |
| * | Break ARM addrmode4 (load/store multiple base address) into its constituent | Jim Grosbach | 2010-11-03 | 1 | -2/+2 |
| * | factor the operand list (and related fields/operations) out of | Chris Lattner | 2010-11-01 | 1 | -9/+7 |
| * | Shifter ops are not always free. Do not fold them (especially to form | Evan Cheng | 2010-10-27 | 1 | -0/+1 |
| * | Provide correct encodings for NEON vcvt, which has its own special immediate ... | Owen Anderson | 2010-10-27 | 1 | -0/+1 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -0/+4 |
| * | ARM mode encoding information for UBFX and SBFX instructions. | Jim Grosbach | 2010-10-15 | 1 | -0/+1 |
| * | Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern | Jim Grosbach | 2010-10-13 | 1 | -0/+1 |
| * | Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. | Jim Grosbach | 2010-10-13 | 1 | -0/+2 |
| * | Fix spelling error. | Cameron Esfahani | 2010-10-12 | 1 | -2/+2 |
| * | trailing whitespace | Jim Grosbach | 2010-10-05 | 1 | -95/+95 |
| * | fix bugs in push/pop segment support, rdar://8407242 | Chris Lattner | 2010-09-08 | 1 | -4/+12 |
| * | remove dead code. | Chris Lattner | 2010-09-01 | 1 | -37/+0 |
| * | Rename sat_shift operand to shift_imm, in preparation for using it for other | Bob Wilson | 2010-08-16 | 1 | -1/+1 |
| * | Cleaned up the for-disassembly-only entries in the arm instruction table so that | Johnny Chen | 2010-08-12 | 1 | -0/+1 |
| * | Move the ARM SSAT and USAT optional shift amount operand out of the | Bob Wilson | 2010-08-11 | 1 | -0/+1 |
| * | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 1 | -0/+1 |
| * | remove option from tablegen for building static header. | Chris Lattner | 2010-07-20 | 1 | -18/+0 |
| * | Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! | Bruno Cardoso Lopes | 2010-07-19 | 1 | -0/+1 |
| * | Start the support for AVX instructions with 256-bit %ymm registers. A couple of | Bruno Cardoso Lopes | 2010-07-09 | 1 | -0/+2 |
| * | Implement the major chunk of PR7195: support for 'callw' | Chris Lattner | 2010-07-07 | 1 | -0/+1 |
| * | Add support for the x86 instructions "pusha" and "popa". | Nico Weber | 2010-06-23 | 1 | -0/+4 |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 | 1 | -0/+1 |
| * | Add instruction encoding for the Neon VMOV immediate instruction. This changes | Bob Wilson | 2010-06-11 | 1 | -4/+1 |
| * | Added a QQQQ register file to model 4-consecutive Q registers. | Evan Cheng | 2010-05-14 | 1 | -0/+1 |
| * | Eliminated the classification of control registers into %ecr_ | Sean Callanan | 2010-05-06 | 1 | -2/+1 |
