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path: root/llvm/utils/TableGen/EDEmitter.cpp
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* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-20/+21
| | | | llvm-svn: 163721
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-2/+5
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+2
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-161/+174
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+1
| | | | | | coprocessor number was removed for this instruction. llvm-svn: 155000
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+1
| | | | llvm-svn: 153935
* Spill DPair registers, not just QPR.Jakob Stoklund Olesen2012-03-281-0/+1
| | | | | | | | | The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. llvm-svn: 153603
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-1/+1
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-1/+1
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-2/+1
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+1
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-0/+2
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Make the EDis tables const.Benjamin Kramer2012-02-111-5/+1
| | | | llvm-svn: 150304
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+2
| | | | | | rdar://10558523 llvm-svn: 147189
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+1
| | | | llvm-svn: 147025
* ARM: NEON SHLL instruction immediate operand range checking.Jim Grosbach2011-12-071-0/+6
| | | | llvm-svn: 146003
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-021-0/+2
| | | | llvm-svn: 145726
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+1
| | | | llvm-svn: 145504
* llvm_unreachable() is not for user diagnostics....Jim Grosbach2011-11-301-1/+1
| | | | llvm-svn: 145465
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+1
| | | | llvm-svn: 145464
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-151-0/+1
| | | | | | integer variants. rdar://10437054 llvm-svn: 144608
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-0/+1
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+1
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+1
| | | | llvm-svn: 142441
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-181-0/+1
| | | | llvm-svn: 142356
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach2011-10-181-0/+2
| | | | llvm-svn: 142321
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach2011-10-171-0/+1
| | | | llvm-svn: 142303
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-171-0/+1
| | | | | | | | NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. llvm-svn: 142293
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+1
| | | | llvm-svn: 141786
* Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-14/+14
| | | | | | This should unbreak the picky buildbots. llvm-svn: 141575
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-3/+3
| | | | | | | | | | The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. llvm-svn: 141562
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+3
| | | | llvm-svn: 141446
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-061-0/+3
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. llvm-svn: 141274
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+1
| | | | llvm-svn: 140560
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+2
| | | | llvm-svn: 140078
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+1
| | | | llvm-svn: 139381
* Thumb2 assembly parsing and encoding for LDRBT.Jim Grosbach2011-09-071-0/+1
| | | | llvm-svn: 139267
* Thumb2 parsing and encoding for LDR(immediate).Jim Grosbach2011-09-071-0/+1
| | | | | | | | | The immediate offset of the non-writeback i8 form (encoding T4) allows negative offsets only. The positive offset form of the encoding is the LDRT instruction. Immediate offsets in the range [0,255] use encoding T3 instead. llvm-svn: 139254
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-0/+1
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach2011-08-241-1/+2
| | | | | | | Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. llvm-svn: 138488
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-0/+1
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-091-0/+1
| | | | | | to tighten our decoding of BFI. llvm-svn: 137168
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-0/+2
| | | | | | range 1-32, with 32 encoded as 0. llvm-svn: 137062
* LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson2011-08-041-0/+1
| | | | | | complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-2/+4
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM: rename addrmode7 to addr_offset_none.Jim Grosbach2011-08-021-1/+1
| | | | | | Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-271-0/+1
| | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. llvm-svn: 136287
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