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path: root/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
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* TableGen: Support physical register inputs > 255Matt Arsenault2019-07-221-6/+16
| | | | | | | This was truncating register value that didn't fit in unsigned char. Switch AMDGPU sendmsg intrinsics to using a tablegen pattern. llvm-svn: 366695
* Recommit r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers ↵Craig Topper2019-03-101-0/+10
| | | | | | | | | | | | | | | | | | for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary." Includes a fix to emit a CheckOpcode for build_vector when immAllZerosV/immAllOnesV is used as a pattern root. This means it can't be used to look through bitcasts when used as a root, but that's probably ok. This extra CheckOpcode will ensure that the first match in the isel table will be a SwitchOpcode which is needed by the caching optimization in the ISel Matcher. Original commit message: Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts. By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up. This removes something like 40,000 bytes from the X86 isel table. Differential Revision: https://reviews.llvm.org/D58595 llvm-svn: 355784
* Revert r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers for ↵Craig Topper2019-03-051-10/+0
| | | | | | | | immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary." This caused the first matcher in the isel table for many targets to Opc_Scope instead of Opc_SwitchOpcode. This leads to a significant increase in isel match failures. llvm-svn: 355433
* [TableGen][SelectionDAG][X86] Add specific isel matchers for ↵Craig Topper2019-03-011-0/+10
| | | | | | | | | | | | | | immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary. Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts. By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up. This removes something like 40,000 bytes from the X86 isel table. Differential Revision: https://reviews.llvm.org/D58595 llvm-svn: 355224
* [SelectionDAG] Add a OPC_CheckChild2CondCode to SelectionDAGISel to remove a ↵Craig Topper2019-02-251-0/+6
| | | | | | | | | | MoveChild and MoveParent pair. OPC_CheckCondCode is always used as operand 2 of a setcc. And its always surrounded by a MoveChild2 and a MoveParent. By having a dedicated opcode for this case we can reduce the number of bytes needed for this pattern from 4 bytes to 2. This saves ~3000 bytes in the X86 table. llvm-svn: 354763
* [Tablegen][DAG]: Fix build breakage when LLVM_ENABLE_DAGISEL_COV=1Aditya Nandakumar2019-02-041-2/+2
| | | | | | | | | | LLVM_ENABLE_DAGISEL_COV can be used to instrument DAGISel tablegen selection code to show which patterns along with Complex patterns were used when selecting instructions. Unfortunately this is turned off by default and was broken but never tested. This required a simple fix (missing new line) to get it to build again. llvm-svn: 353091
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* TableGen/ISel: Allow PatFrag predicate code to access captured operandsNicolai Haehnle2018-11-301-27/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992
* [SelectionDAG] Add a isel matcher op to check the type of node results other ↵Craig Topper2017-11-221-5/+8
| | | | | | | | than result 0. I plan to use this to check the type of the mask result of masked gathers in the X86 backend. llvm-svn: 318820
* Allow separation of declarations and definitions in <Target>ISelDAGToDAG.incKrzysztof Parzyszek2017-11-101-17/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to include the member function declarations in the instruction selector class separately from the member bodies. Defining GET_DAGISEL_DECL macro to any value will only include the member declarations. To include bodies, define GET_DAGISEL_BODY macro to be the selector class name. Example: class FooDAGToDAGISel : public SelectionDAGISel { // Pull in declarations only. #define GET_DAGISEL_DECL #include "FooISelDAGToDAG.inc" }; // Include the function bodies (with names qualified with the provided // class name). #define GET_DAGISEL_BODY FooDAGToDAGISel #include "FooISelDAGToDAG.inc" When neither of the two macros are defined, the function bodies are emitted inline (in the same way as before this patch). Differential Revision: https://reviews.llvm.org/D39596 llvm-svn: 317903
* [TableGen] Add an extra blank line to DAGISel output file to separate functions.Craig Topper2017-11-031-1/+1
| | | | llvm-svn: 317298
* Strip trailing whitespaceSimon Pilgrim2017-10-061-5/+5
| | | | llvm-svn: 315070
* [TableGen] Generate formatted DAGISelEmitter without relying on ↵Craig Topper2017-09-191-91/+93
| | | | | | | | | | | | | | formatted_raw_ostream. The generated DAG isel file currently makes use of formatted_raw_ostream primarily for generating a hierarchical representation while also skipping over the initial comment that contains the current index. It was reported in D37957 that this formatting might be slow due to the need to keep track of column numbers by monitoring all the written data for new lines. This patch attempts to rewrite the emitter to make use of simpler formatting mechanisms to generate a fairly similar output. The main difference is that the number in the index comment is now right justified and padded with spaces inside the comment. Previously we appended the spaces after the comment. Differential Revision: https://reviews.llvm.org/D37966 llvm-svn: 313674
* [tablegen] Use categories on options that only matter to one emitter.Daniel Sanders2017-03-271-4/+6
| | | | | | | | | | | | | | | | Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
* [SelectionDAG] Make SelectCode return voidJoey Gouly2017-03-091-2/+1
| | | | | | | | | | | SelectCode has been returning nullptr since 182dac0 ("SDAG: Make SelectCodeCommon return void", 2016-05-10). Make SelectCode also return void instead, as all callers have been updated. Patch by Sven van Haastregt. Review: https://reviews.llvm.org/D30497 llvm-svn: 297377
* [Tablegen] Instrumenting table gen DAGGenISelDAGAditya Nandakumar2017-02-141-4/+135
| | | | | | | | | | To help assist in debugging ISEL or to prioritize GlobalISel backend work, this patch adds two more tables to <Target>GenISelDAGISel.inc - one which contains the patterns that are used during selection and the other containing include source location of the patterns Enabled through CMake varialbe LLVM_ENABLE_DAGISEL_COV llvm-svn: 295081
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-2/+3
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* SDAG: Remove OPC_MarkGlueResults and associated logic. NFCJustin Bogner2016-05-051-10/+0
| | | | | | | | | This opcode never happens in practice, and yet the logic we have in place to handle it would be undefined behaviour if we ever executed it. Remove it rather than trying to refactor code that's never reached. llvm-svn: 268692
* [CodeGen] Add some space optimized forms of EmitNode and MorphNodeTo that ↵Craig Topper2016-05-031-5/+12
| | | | | | | | implicitly indicate the number of result VTs. This shaves about 16K off the X86 matching table taking it down to about 470K. Overall this reduces the llc binary size with all in-tree targets by about 40K. llvm-svn: 268365
* [CodeGen] Add OPC_MoveChild0-OPC_MoveChild7 opcodes to isel matching tables ↵Craig Topper2016-05-021-3/+10
| | | | | | to optimize table size. Shaves about 12K off the X86 matcher table. llvm-svn: 268209
* [CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel ↵Craig Topper2016-03-071-2/+2
| | | | | | matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC llvm-svn: 262815
* [TableGen][DAGISel] Dedup predicates with same code to run. NFCI.Ahmed Bougacha2015-08-271-4/+25
| | | | | | | | | | | I locally hit the 255 limit, but a lot of these are redundant: each predicate coming from a different record was allocated a new number, even when we already emitted the same code for another predicate. Instead, re-use numbers and emit the predicate code only once. This reduces the total text size of *DAGISel.cpp.o by ~1%. llvm-svn: 246208
* [TableGen] Remove dead code. NFC.Ahmed Bougacha2015-08-271-7/+0
| | | | | | The only user of this was removed in r129670. llvm-svn: 246176
* Teach raw_ostream to accept SmallString.Yaron Keren2015-03-101-2/+2
| | | | | | | | | | | | | | Saves adding .str() call to any raw_ostream << SmallString usage and a small step towards making .str() consistent in the ADTs by removing one of the SmallString::str() use cases, discussion at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141013/240026.html I'll update the Phabricator patch http://reviews.llvm.org/D6372 for review of the Twine SmallString support, it's more complex than this one. llvm-svn: 231763
* Use unique_ptr to handle ownership of TreePatterns in ↵David Blaikie2014-11-131-1/+1
| | | | | | | | | CodeGenDAGPatterns::PatternFragments We might be able to use unique_ptr to handle ownership of the TreePatternNodes too - looking into that next. llvm-svn: 221928
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-2/+2
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-7/+7
| | | | | | class. llvm-svn: 203378
* Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes ↵Craig Topper2014-02-051-0/+9
| | | | | | from X86 matcher table. llvm-svn: 200821
* Couple minor formatting fixes to the XXXGenDAGISel.inc files.Craig Topper2014-01-301-2/+1
| | | | llvm-svn: 200459
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-051-0/+7
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 192026
* Revert r191940 to see if it fixes the build bots.Craig Topper2013-10-041-7/+0
| | | | llvm-svn: 191941
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-041-0/+7
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 191940
* Add missing index comments to the left side of the DAG ISel matcher table ↵Craig Topper2013-09-221-2/+6
| | | | | | for each individual case of SwitchOpcode/Type. llvm-svn: 191181
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | llvm-svn: 174390
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-1/+1
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-5/+6
| | | | llvm-svn: 164002
* TblGen: Tweak to pretty-print DAGISel.inc a bit better.Jim Grosbach2012-07-181-2/+2
| | | | llvm-svn: 160463
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-6/+5
| | | | llvm-svn: 149814
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Rework our internal representation of node predicates to expose moreChris Lattner2011-04-171-27/+19
| | | | | | | | structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. llvm-svn: 129670
* Teach TableGen to pre-calculate register enum values when creating theJim Grosbach2011-03-111-23/+16
| | | | | | | | | | | CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 llvm-svn: 127456
* trailing whitespace.Jim Grosbach2011-03-011-79/+79
| | | | llvm-svn: 126733
* Generalize the register matching code in DAGISel a bit.Jim Grosbach2011-03-011-19/+39
| | | | llvm-svn: 126731
* flags -> glue for selectiondagChris Lattner2010-12-231-4/+4
| | | | llvm-svn: 122509
* sdisel flag -> glue.Chris Lattner2010-12-231-2/+2
| | | | llvm-svn: 122507
* continue renaming flag -> glue.Chris Lattner2010-12-231-5/+5
| | | | llvm-svn: 122506
* Rework passing parent pointers into complexpatterns, I forgotChris Lattner2010-09-211-2/+3
| | | | | | | | that complex patterns are matched after the entire pattern has a structural match, therefore the NodeStack isn't in a useful state when the actual call to the matcher happens. llvm-svn: 114489
* just like they can opt into getting the root of the pattern beingChris Lattner2010-09-211-1/+6
| | | | | | | matched, allow ComplexPatterns to opt into getting the parent node of the operand being matched. llvm-svn: 114472
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-1/+7
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* Moar words!Eric Christopher2010-08-061-1/+1
| | | | llvm-svn: 110422
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