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path: root/llvm/utils/TableGen/DAGISelEmitter.cpp
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* Lots of improvements to the new dagisel emitter. This gets it toChris Lattner2010-02-211-72/+10
| | | | | | | | | | | | | | | | | | | the point where it is to the 95% feature complete mark, it just needs result updating to be done (then testing, optimization etc). More specificallly, this adds support for chain and flag handling on the result nodes, support for sdnodexforms, support for variadic nodes, memrefs, pinned physreg inputs, and probably lots of other stuff. In the old DAGISelEmitter, this deletes the dead code related to OperatorMap, cleans up a variety of dead stuff handling "implicit remapping" from things like globaladdr -> targetglobaladdr (which is no longer used because globaladdr always needs to be legalized), and some minor formatting fixes. llvm-svn: 96716
* start sketching out the structure of code for result emission generation.Chris Lattner2010-02-181-1/+1
| | | | | | Nothing real here yet. llvm-svn: 96575
* fit in 80 colsChris Lattner2010-02-181-7/+11
| | | | llvm-svn: 96541
* redisable this to save people a small amount of build time.Chris Lattner2010-02-171-1/+1
| | | | llvm-svn: 96497
* move isOnlyReachableByFallthrough out of MachineBasicBlock into AsmPrinter,Chris Lattner2010-02-171-1/+1
| | | | | | | and add a sparc implementation that knows about delay slots. Patch by Nathan Keynes! llvm-svn: 96492
* sink special case "cannotyetselect" for intrinsics out of the Chris Lattner2010-02-171-14/+2
| | | | | | tblgen splatted code into the implementation. llvm-svn: 96460
* simplify IsChainCompatible codegen, add comments. no Chris Lattner2010-02-171-4/+2
| | | | | | functionality change. llvm-svn: 96453
* make the new isel generator plop out a CheckComplexPattern functionChris Lattner2010-02-171-1/+1
| | | | | | | for evaluating complex patterns. Some cleanup has to happen before this can be used though. llvm-svn: 96419
* clean up some code, eliminate NodeIsComplexPattern, whichChris Lattner2010-02-161-18/+5
| | | | | | does the same thing as getComplexPatternInfo. llvm-svn: 96411
* fix indentationChris Lattner2010-02-161-62/+66
| | | | llvm-svn: 96409
* fix rdar://7653908, a crash on a case where we would fold a loadChris Lattner2010-02-161-39/+27
| | | | | | | | | | into a roundss intrinsic, producing a cyclic dag. The root cause of this is badness handling ComplexPattern nodes in the old dagisel that I noticed through inspection. Eliminate a copy of the of the code that handled ComplexPatterns by making EmitChildMatchCode call into EmitMatchCode. llvm-svn: 96408
* change dag isel emitter to only call 'IsProfitableToFold' on nodesChris Lattner2010-02-161-3/+13
| | | | | | | | with chains. On interior nodes that lead up to them, we just directly check that there is a single use. This generates slightly more efficient code. llvm-svn: 96366
* mark all the generated node predicates 'const'.Chris Lattner2010-02-161-2/+2
| | | | llvm-svn: 96337
* remove now dead code and fixme.Chris Lattner2010-02-161-2/+0
| | | | llvm-svn: 96333
* remove dead code. This is never generated for any targets in mainline.Chris Lattner2010-02-161-15/+0
| | | | llvm-svn: 96332
* add support for the new isel matcher to generate Chris Lattner2010-02-161-0/+2
| | | | | | (isprofitable|islegal)tofold checks. llvm-svn: 96331
* Split SelectionDAGISel::IsLegalAndProfitableToFold toEvan Cheng2010-02-151-4/+6
| | | | | | | | IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use. This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses. llvm-svn: 96255
* Check in the first big step of rewriting DAGISelEmitter to Chris Lattner2010-02-151-2/+24
| | | | | | | | | | | | | | | | | | | produce a table based matcher instead of gobs of C++ Code. Though it's not done yet, the shrinkage seems promising, the table for the X86 ISel is 75K and still has a lot of optimization to come (compare to the ~1.5M of .o generated the old way, much of which will go away). The code is currently disabled by default (the #if 0 in DAGISelEmitter.cpp). When enabled it generates a dead SelectCode2 function in the DAGISel Header which will eventually replace SelectCode. There is still a lot of stuff left to do, which are documented with a trail of FIXMEs. llvm-svn: 96215
* clean up a bunch of code, move some random predicatesChris Lattner2010-02-141-100/+43
| | | | | | on TreePatternNode to be methods on TreePatternNode. llvm-svn: 96197
* remove the DisablePatternForFastISel predicate, which is a checkChris Lattner2010-02-141-24/+3
| | | | | | | | that predated -fast-isel which attempted to speed up the dag pattern matchers at -O0. Since fast-isel is around, this is basically obsolete and removing it shrinks the generated dag isels. llvm-svn: 96188
* pull a bunch of huge inline methods in the PatternCodeEmitter Chris Lattner2010-02-131-866/+890
| | | | | | class out of line. llvm-svn: 96113
* Change SelectCode's argument from SDValue to SDNode *, to make it moreDan Gohman2010-01-051-75/+102
| | | | | | | | | clear what information these functions are actually using. This is also a micro-optimization, as passing a SDNode * around is simpler than passing a { SDNode *, int } by value or reference. llvm-svn: 92564
* Replace some special-case code which probably was buggy with an assertionDan Gohman2010-01-041-6/+1
| | | | | | verifying that the special case does not occur. llvm-svn: 92504
* Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman2010-01-041-9/+3
| | | | | | for a refactoring I'm working on. llvm-svn: 92503
* Fix a comment.Dan Gohman2009-12-191-2/+2
| | | | llvm-svn: 91741
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-1/+0
| | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. llvm-svn: 89711
* Implement DISABLE_INLINE for MSVC. This required changing the position in allBenjamin Kramer2009-11-141-5/+4
| | | | | | forward declaration and patching tblgen to emit it right. Patch by Amine Khaldi! llvm-svn: 88798
* It is invalid to infer the value type from the result #0 of the nodeAnton Korobeynikov2009-11-081-1/+1
| | | | | | since the instruction might use the other result of different type. llvm-svn: 86462
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+1
| | | | llvm-svn: 85556
* Move some code from being emitted as boilerplate duplicated in everyDan Gohman2009-10-291-58/+0
| | | | | | *ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp. llvm-svn: 85530
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-1/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Report errors correctly for unselected target intrinsics.Jakob Stoklund Olesen2009-10-151-2/+10
| | | | llvm-svn: 84193
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-18/+11
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-251-3/+3
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Eliminate some unnecessary implicit constructors in generated DAG ISel code.Owen Anderson2009-09-111-1/+1
| | | | | | Partial fix for PR4946. llvm-svn: 81518
* Change Pass::print to take a raw ostream instead of std::ostream,Chris Lattner2009-08-231-1/+1
| | | | | | update all code that this affects. llvm-svn: 79830
* remove some DOUTsChris Lattner2009-08-231-4/+4
| | | | llvm-svn: 79821
* Record variable debug info at ISel time directly.Devang Patel2009-08-221-18/+0
| | | | llvm-svn: 79742
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-44/+44
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-48/+48
| | | | | | own struct type. llvm-svn: 78610
* strength reduce anonymous namespace to static.Chris Lattner2009-08-071-5/+2
| | | | llvm-svn: 78417
* Remove itohexstr, which only had one user.Daniel Dunbar2009-07-301-1/+2
| | | | llvm-svn: 77613
* make ptr_rc derive from a new PointerLikeRegClass tblgen class.Chris Lattner2009-07-291-1/+1
| | | | llvm-svn: 77503
* Convert more abort() calls to llvm_report_error().Torok Edwin2009-07-081-8/+7
| | | | | | Also remove trailing semicolon. llvm-svn: 75027
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-16/+16
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-49/+15
| | | | llvm-svn: 72712
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-011-15/+49
| | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. llvm-svn: 72707
* Slightly improve generated code in a degenerate case.Dale Johannesen2009-05-121-0/+8
| | | | | | Should remove a warning from MSVC. llvm-svn: 71603
* Quotes are used for including llvm headers, rather than angles.Dan Gohman2009-05-041-1/+1
| | | | llvm-svn: 70879
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-291-1/+1
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
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