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path: root/llvm/utils/TableGen/DAGISelEmitter.cpp
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* Add patterns for CALL32m and CALL64m. They aren't matched in mostDan Gohman2008-05-291-6/+5
| | | | | | | | | | | | cases due to an isel deficiency already noted in lib/Target/X86/README.txt, but they can be matched in this fold-call.ll testcase, for example. This is interesting mainly because it exposes a tricky tblgen bug; tblgen was incorrectly computing the starting index for variable_ops in the case of a complex pattern. llvm-svn: 51706
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-19/+28
| | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). llvm-svn: 51699
* Do not generate by TableGen the hard-coded standard, target-independent part ofRoman Levenstein2008-05-141-140/+3
| | | | | | | | | | | | | | | DAG instruction selectors. Introudce a dedicated header file for this part: include/llvm/CodeGen/DAGISelHeader.h TableGen now only generates the include preprocessor directive to include this new header. This is a preparation for supporting multiple implementations of instruction selectors in the future. Reviewed and approved by Evan and Dan. llvm-svn: 51102
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-2/+8
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-131-11/+6
| | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. llvm-svn: 48329
* De-tabify.Bill Wendling2008-02-261-7/+7
| | | | llvm-svn: 47595
* Unbreak build with gcc 4.3: provide missed includes and silence most ↵Anton Korobeynikov2008-02-201-1/+2
| | | | | | annoying warnings. llvm-svn: 47367
* Make tblgen a little smarter about constants smaller than i32. Currently,Scott Michel2008-02-151-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | tblgen will complain if a sign-extended constant does not fit into a data type smaller than i32, e.g., i16. This causes a problem when certain hex constants are used, such as 0xff for byte masks or immediate xor values. tblgen will try the sign-extended value first and, if the sign extended value would overflow, it tries to see if the unsigned value will fit. Consequently, a software developer can now safely incant: (XORHIr16 R16C:$rA, 0xffff) which is somewhat clearer and more informative than incanting: (XORHIr16 R16C:$rA, (i16 -1)) even if the two are bitwise equivalent. Tblgen also outputs the 64-bit unsigned constant in the generated ISel code when getTargetConstant() is invoked. llvm-svn: 47188
* Change how FP immediates are handled. Nate Begeman2008-02-141-0/+13
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Re-apply the memory operand changes, with a fix for the staticDan Gohman2008-02-061-0/+28
| | | | | | | | initializer problem, a minor tweak to the way the DAGISelEmitter finds load/store nodes, and a renaming of the new PseudoSourceValue objects. llvm-svn: 46827
* Fix PR1975: dag isel emitter produces patterns that isel wrong flag result.Evan Cheng2008-02-051-4/+21
| | | | llvm-svn: 46776
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-3/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* Change the 'global modification' APIs in SelectionDAG to take a newChris Lattner2008-02-031-22/+35
| | | | | | | | | | DAGUpdateListener object pointer instead of just returning a vector of deleted nodes. This makes the interfaces more efficient (no more allocating a vector [at least a malloc], filling it in, then walking it) and more clean. This also allows the client to be notified of nodes that are *changed* but not deleted. llvm-svn: 46677
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+25
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and ↵Evan Cheng2008-01-311-27/+0
| | | | | | re-commit. llvm-svn: 46623
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-4/+7
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb2008-01-311-4/+10
| | | | | | | | | | complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. llvm-svn: 46606
* Create a new class, MemOperand, for describing memory referencesDan Gohman2008-01-311-0/+27
| | | | | | | | | | | | | | | | in the backend. Introduce a new SDNode type, MemOperandSDNode, for holding a MemOperand in the SelectionDAG IR, and add a MemOperand list to MachineInstr, and code to manage them. Remove the offset field from SrcValueSDNode; uses of SrcValueSDNode that were using it are all all using MemOperandSDNode now. Also, begin updating some getLoad and getStore calls to use the PseudoSourceValue objects. Most of this was written by Florian Brander, some reorganization and updating to TOT by me. llvm-svn: 46585
* Fix to bug 1951: tblgen gratuitously renames variables when no temporary wasScott Michel2008-01-291-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | generated. This feature would only show up in fairly complex patterns, such as this one in CellSPU: def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)), (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>; which generated the following emit code: SDNode *Emit_0(const SDOperand &N, unsigned Opc0, unsigned Opc1, MVT::ValueType VT0, MVT::ValueType VT1) DISABLE_INLINE { SDOperand N0 = N.getOperand(0); SDOperand N00 = N0.getOperand(0); SDOperand N01 = N0.getOperand(1); SDOperand N1 = N.getOperand(1); SDOperand N10 = N1.getOperand(0); SDOperand N11 = N1.getOperand(1); SDOperand Tmp3(CurDAG->getTargetNode(Opc0, VT0, N00), 0); return CurDAG->SelectNodeTo(N.Val, Opc1, VT1, Tmp3, Tmp2); /* Tmp2 s/b N00 */ } Tested against the test suites without incident. llvm-svn: 46487
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-071-1/+1
| | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. llvm-svn: 45687
* improve const correctness.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45646
* rename CodegenDAGPatterns -> CodeGenDAGPatternsChris Lattner2008-01-061-16/+16
| | | | llvm-svn: 45641
* now that computing CodegenDAGPatterns doesn't implicitly print stuff Chris Lattner2008-01-051-28/+23
| | | | | | | | | out, DAGISelEmitter can compute it in its ctor, which simplifies some code. Now we can use CodegenDAGPatterns in other parts of tblgen that want access to dag pattern info, woo! llvm-svn: 45636
* move Node Transformation printing from CodeGenDAGPatterns -> DAGISelEmitter.Chris Lattner2008-01-051-1/+35
| | | | | | | The only difference in output is that we now print them in alphabetical order instead of reverse alphabetical order. llvm-svn: 45635
* move predicate printing code from CodeGenDAGPatterns -> DAGISelEmitter.Chris Lattner2008-01-051-2/+52
| | | | llvm-svn: 45634
* fix a fixme by improving const correctness.Chris Lattner2008-01-051-20/+21
| | | | llvm-svn: 45633
* change getQualifiedName to be a global function.Chris Lattner2008-01-051-2155/+103
| | | | | | | | Split the pattern parsing code out from the dag isel emitter into it's own file. No functionality change. llvm-svn: 45632
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* switch some calls to SelectionDAG::getTargetNode to useChris Lattner2007-10-241-4/+7
| | | | | | | | the one that takes an operand list instead of explicit operands. There is one left though, the more interesting one :) llvm-svn: 43290
* One mundane change: Change ReplaceAllUsesOfValueWith to *optionally* Chris Lattner2007-10-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | take a deleted nodes vector, instead of requiring it. One more significant change: Implement the start of a legalizer that just works on types. This legalizer is designed to run before the operation legalizer and ensure just that the input dag is transformed into an output dag whose operand and result types are all legal, even if the operations on those types are not. This design/impl has the following advantages: 1. When finished, this will *significantly* reduce the amount of code in LegalizeDAG.cpp. It will remove all the code related to promotion and expansion as well as splitting and scalarizing vectors. 2. The new code is very simple, idiomatic, and modular: unlike LegalizeDAG.cpp, it has no 3000 line long functions. :) 3. The implementation is completely iterative instead of recursive, good for hacking on large dags without blowing out your stack. 4. The implementation updates nodes in place when possible instead of deallocating and reallocating the entire graph that points to some mutated node. 5. The code nicely separates out handling of operations with invalid results from operations with invalid operands, making some cases simpler and easier to understand. 6. The new -debug-only=legalize-types option is very very handy :), allowing you to easily understand what legalize types is doing. This is not yet done. Until the ifdef added to SelectionDAGISel.cpp is enabled, this does nothing. However, this code is sufficient to legalize all of the code in 186.crafty, olden and freebench on an x86 machine. The biggest issues are: 1. Vectors aren't implemented at all yet 2. SoftFP is a mess, I need to talk to Evan about it. 3. No lowering to libcalls is implemented yet. 4. Various operations are missing etc. 5. There are FIXME's for stuff I hax0r'd out, like softfp. Hey, at least it is a step in the right direction :). If you'd like to help, just enable the #ifdef in SelectionDAGISel.cpp and compile code with it. If this explodes it will tell you what needs to be implemented. Help is certainly appreciated. Once this goes in, we can do three things: 1. Add a new pass of dag combine between the "type legalizer" and "operation legalizer" passes. This will let us catch some long-standing isel issues that we miss because operation legalization often obfuscates the dag with target-specific nodes. 2. We can rip out all of the type legalization code from LegalizeDAG.cpp, making it much smaller and simpler. When that happens we can then reimplement the core functionality left in it in a much more efficient and non-recursive way. 3. Once the whole legalizer is non-recursive, we can implement whole-function selectiondags maybe... llvm-svn: 42981
* Fix typos.Evan Cheng2007-10-121-5/+5
| | | | llvm-svn: 42896
* Rename keyword "modify" -> "implicit".Evan Cheng2007-09-251-6/+6
| | | | llvm-svn: 42282
* Bug fix and minor clean up of generated code.Evan Cheng2007-09-171-29/+18
| | | | llvm-svn: 42069
* Initial support for multi-result patterns:Evan Cheng2007-09-121-56/+95
| | | | | | | | | | | | 1. [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), (modify EFLAGS)] This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS. 2. def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()> Similar to #1 except this is used for def : Pat patterns. llvm-svn: 41897
* Allow set operators with multiple destinations, i.e. (set x, y, (op a, b)).Evan Cheng2007-09-111-22/+25
| | | | llvm-svn: 41861
* TableGen no longer emit CopyFromReg nodes for implicit results in physicalEvan Cheng2007-09-071-44/+15
| | | | | | registers. The scheduler is now responsible for emitting them. llvm-svn: 41781
* Always check the type of node. This prevents situations such as selecting ↵Evan Cheng2007-09-041-36/+30
| | | | | | 32-bit rotate target instruction for a 64-bit node when 64-bit pattern is missing. llvm-svn: 41710
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-1/+30
| | | | | | MBB's. PR1350 llvm-svn: 40518
* A minor simplication in the generated code.Dan Gohman2007-07-241-2/+2
| | | | llvm-svn: 40479
* No need for noResults anymore.Evan Cheng2007-07-201-3/+2
| | | | llvm-svn: 40075
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-1/+6
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Refactor code to add initial support for OptionalDefOperand.Evan Cheng2007-07-061-53/+63
| | | | llvm-svn: 37933
* Teach DAGISelEmitter about zero_reg.Evan Cheng2007-07-051-1/+8
| | | | llvm-svn: 37900
* silence warning when assertions are disabled.Chris Lattner2007-06-191-2/+1
| | | | llvm-svn: 37654
* Fix CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll, the other recentChris Lattner2007-05-151-5/+7
| | | | | | patches are also needed. llvm-svn: 37070
* PredicateOperand related bug fix.Evan Cheng2007-05-151-1/+3
| | | | llvm-svn: 37060
* If a PredicateOperand has an empty ExecuteAlways field, treat it as if a ↵Evan Cheng2007-05-081-4/+9
| | | | | | normal operand for isel. llvm-svn: 36946
* bugfix: remember that ResNode was declared.Lauro Ramos Venancio2007-04-261-2/+3
| | | | llvm-svn: 36477
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-2/+5
| | | | | | X86 32 bits. llvm-svn: 36283
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