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path: root/llvm/utils/TableGen/DAGISelEmitter.cpp
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* Fix a comment.Dan Gohman2009-12-191-2/+2
| | | | llvm-svn: 91741
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-1/+0
| | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. llvm-svn: 89711
* Implement DISABLE_INLINE for MSVC. This required changing the position in allBenjamin Kramer2009-11-141-5/+4
| | | | | | forward declaration and patching tblgen to emit it right. Patch by Amine Khaldi! llvm-svn: 88798
* It is invalid to infer the value type from the result #0 of the nodeAnton Korobeynikov2009-11-081-1/+1
| | | | | | since the instruction might use the other result of different type. llvm-svn: 86462
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+1
| | | | llvm-svn: 85556
* Move some code from being emitted as boilerplate duplicated in everyDan Gohman2009-10-291-58/+0
| | | | | | *ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp. llvm-svn: 85530
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-1/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Report errors correctly for unselected target intrinsics.Jakob Stoklund Olesen2009-10-151-2/+10
| | | | llvm-svn: 84193
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-18/+11
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-251-3/+3
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Eliminate some unnecessary implicit constructors in generated DAG ISel code.Owen Anderson2009-09-111-1/+1
| | | | | | Partial fix for PR4946. llvm-svn: 81518
* Change Pass::print to take a raw ostream instead of std::ostream,Chris Lattner2009-08-231-1/+1
| | | | | | update all code that this affects. llvm-svn: 79830
* remove some DOUTsChris Lattner2009-08-231-4/+4
| | | | llvm-svn: 79821
* Record variable debug info at ISel time directly.Devang Patel2009-08-221-18/+0
| | | | llvm-svn: 79742
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-44/+44
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-48/+48
| | | | | | own struct type. llvm-svn: 78610
* strength reduce anonymous namespace to static.Chris Lattner2009-08-071-5/+2
| | | | llvm-svn: 78417
* Remove itohexstr, which only had one user.Daniel Dunbar2009-07-301-1/+2
| | | | llvm-svn: 77613
* make ptr_rc derive from a new PointerLikeRegClass tblgen class.Chris Lattner2009-07-291-1/+1
| | | | llvm-svn: 77503
* Convert more abort() calls to llvm_report_error().Torok Edwin2009-07-081-8/+7
| | | | | | Also remove trailing semicolon. llvm-svn: 75027
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-16/+16
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-49/+15
| | | | llvm-svn: 72712
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-011-15/+49
| | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. llvm-svn: 72707
* Slightly improve generated code in a degenerate case.Dale Johannesen2009-05-121-0/+8
| | | | | | Should remove a warning from MSVC. llvm-svn: 71603
* Quotes are used for including llvm headers, rather than angles.Dan Gohman2009-05-041-1/+1
| | | | llvm-svn: 70879
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-291-1/+1
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Second attempt:Bill Wendling2009-04-291-1/+1
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-281-1/+1
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-281-1/+1
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-0/+9
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.Dan Gohman2009-04-031-21/+0
| | | | | | | Note that these are distinct from TargetInstrInfo::INSERT_SUBREG and TargetInstrInfo::EXTRACT_SUBREG, which are used. llvm-svn: 68355
* fix a few spelling errors and typosJim Grosbach2009-03-261-1/+1
| | | | llvm-svn: 67758
* Use 'bool' for FoundRCJim Grosbach2009-03-261-2/+2
| | | | llvm-svn: 67750
* Modify getRegisterValueType() to allow for a register being in mutlipleJim Grosbach2009-03-251-5/+26
| | | | | | | | register classes. Before, MVT::Other would be returned anytime a reg was in multiple register classes. Now, MVT::Other is only returned if the types for those register classes differ. llvm-svn: 67714
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-061-1/+2
| | | | | | | its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
* Remove a non-DebugLoc version of getNode.Dale Johannesen2009-02-051-2/+2
| | | | llvm-svn: 63889
* Remove non-DebugLoc forms of CopyToReg and CopyFromReg.Dale Johannesen2009-02-041-0/+1
| | | | | | Adjust callers. llvm-svn: 63789
* Explain why this is here.Bill Wendling2009-01-291-0/+1
| | | | llvm-svn: 63342
* - Add DebugLoc to getTargetNode(). Bill Wendling2009-01-291-0/+3
| | | | | | | | | - Modify TableGen to add the DebugLoc when calling getTargetNode. (The light-weight wrappers are only temporary. The non-DebugLoc version will be removed once the whole debug info stuff is finished with.) llvm-svn: 63273
* Move the code that starts printing the Select_* functionsDan Gohman2009-01-291-3/+3
| | | | | | | | after the code that sorts the patterns. This doesn't affect the output, but it makes the code a little easier to follow. llvm-svn: 63265
* Avoid triggering an assertion failure when an instruction patternDan Gohman2009-01-161-1/+2
| | | | | | is a leaf node. Patch by Brandner! llvm-svn: 62361
* Add support for instructions with multiple ComplexPatterns, byDan Gohman2009-01-161-7/+7
| | | | | | | adding more information to the temporary variables names so that they don't conflict. llvm-svn: 62296
* Delete an unused variable and simplify the code.Dan Gohman2009-01-051-10/+7
| | | | llvm-svn: 61732
* Use dyn_cast intead of isa + cast in the generated DAGISel code. ThisDan Gohman2008-12-191-7/+13
| | | | | | reduces the amount of code slightly when assertions are enabled. llvm-svn: 61249
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-1/+1
| | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. llvm-svn: 60459
* On x86 favors folding short immediate into some arithmetic operations (e.g. ↵Evan Cheng2008-11-271-2/+2
| | | | | | | | | | | | | | | add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size. e.g. movl 4(%esp), %eax addl $4, %eax is 2 bytes shorter than movl $4, %eax addl 4(%esp), %eax llvm-svn: 60139
* Use an assert to check that SelectCode isn't called onDan Gohman2008-11-051-5/+4
| | | | | | nodes that are already selected. llvm-svn: 58763
* Eliminate the ISel priority queue, which used the topological order for aDan Gohman2008-11-051-30/+5
| | | | | | | | | | | | | | | | | | | | | | | | priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. llvm-svn: 58748
* Have TableGen emit setSubgraphColor calls under control of a -gen-debugDavid Greene2008-10-271-5/+45
| | | | | | | | flag. Then in a debugger developers can set breakpoints at these calls to see waht is about to be selected and what the resulting subgraph looks like. This really helps when debugging instruction selection. llvm-svn: 58278
* Use INT64_C to emit constant values, to avoid problems withDan Gohman2008-10-171-2/+3
| | | | | | | | constants that don't fit in an int. This fixes "this decimal constant is unsigned only in ISO C90" warnings. llvm-svn: 57668
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