summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/CodeGenTarget.h
Commit message (Collapse)AuthorAgeFilesLines
* [GlobalISel][Tablegen] Assign small opcodes to pseudosRoman Tereshin2018-05-231-0/+12
| | | | | | | | | | | | | | Sort pseudo instructions first while emitting enum's for target instructions info. That puts them close to each other and to generic G_* opcodes for GlobalISel. This makes it easier to build small jump tables over opcodes that could be directly embedded into MatchTable's Tablegen'erated for GlobalISel's InstructionSelect. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D47240 llvm-svn: 333135
* [Tablegen] Tidying up InstRegexOp a little, NFCRoman Tereshin2018-05-231-5/+5
| | | | | | Differential Review: https://reviews.llvm.org/D47240 llvm-svn: 333121
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [TableGen] Add a way of getting the number of generic opcodes without ↵Benjamin Kramer2018-01-241-0/+3
| | | | | | | | | | including modular CodeGen headers. This is a bit of a hack, but removes a cycle that broke modular builds of LLVM. Of course the cycle is still there in form of a dependency on the .def file. llvm-svn: 323383
* TableGen: Allow setting SDNodeProperties on intrinsicsMatt Arsenault2017-12-201-19/+1
| | | | | | | | | | | | | | | | | Allows preserving MachineMemOperands on intrinsics through selection. For reasons I don't understand, this is a static property of the pattern and the selector deliberately goes out of its way to drop if not present. Intrinsics already inherit from SDPatternOperator allowing them to be used directly in instruction patterns. SDPatternOperator has a list of SDNodeProperty, but you currently can't set them on the intrinsic. Without SDNPMemOperand, when the node is selected any memory operands are always dropped. Allowing setting this on the intrinsics avoids needing to introduce another equivalent target node just to have SDNPMemOperand set. llvm-svn: 321212
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-1/+1
| | | | | | namespace. NFC llvm-svn: 307362
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+1
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-091-1/+2
| | | | | | | | | represents a relocatable immediate.", with a fix for 32-bit x86. Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions that take a global address operand. llvm-svn: 286420
* Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-091-2/+1
| | | | | | | | | represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
* X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable ↵Peter Collingbourne2016-11-091-1/+2
| | | | | | | | | | | | | | | immediate. A relocatable immediate is either an immediate operand or an operand that can be relocated by the linker to an immediate, such as a regular symbol in non-PIC code. Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands of type "imm32_su". Remove a number of now-redundant patterns. Differential Revision: https://reviews.llvm.org/D25812 llvm-svn: 286384
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-1/+1
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* TableGen: Use StringRef instead of std::stringMatt Arsenault2016-05-251-2/+2
| | | | llvm-svn: 270741
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-3/+0
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* [TableGen] Return ArrayRef instead of a std::vector reference from ↵Craig Topper2016-01-171-2/+2
| | | | | | getInstructionsByEnumValue(). NFC llvm-svn: 258018
* [TableGen] Use std::find instead of a manual loop. NFCCraig Topper2016-01-171-3/+1
| | | | llvm-svn: 258017
* Use make_range to reduce mentions of iterator type. NFCCraig Topper2015-12-061-1/+1
| | | | llvm-svn: 254872
* Use unique_ptr instead of DeleteContainerSeconds.Craig Topper2014-12-101-4/+5
| | | | llvm-svn: 223918
* Use unique_ptr to simplify deletion.Craig Topper2014-11-281-2/+2
| | | | llvm-svn: 222929
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* iterator_range accessor for CodeGenTarget instruction list.Jim Grosbach2014-04-181-0/+3
| | | | llvm-svn: 206551
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-171-0/+4
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-171-3/+3
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-2/+2
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen2012-08-231-0/+4
| | | | | | | | | | | | Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. llvm-svn: 162460
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-1/+7
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-011-4/+0
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. llvm-svn: 151814
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-291-0/+4
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. llvm-svn: 151760
* Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel2012-01-091-0/+10
| | | | | | | AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-4/+0
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-0/+7
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-4/+0
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen2011-06-151-64/+2
| | | | | | No functional change intended. llvm-svn: 133029
* Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen2011-06-111-4/+1
| | | | | | | Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. llvm-svn: 132865
* Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen2011-06-101-19/+4
| | | | | | | Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. llvm-svn: 132849
* Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen2011-05-071-0/+3
| | | | | | | The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. llvm-svn: 131058
* Trailing whitespace.Jim Grosbach2011-03-111-13/+13
| | | | llvm-svn: 127447
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-3/+3
| | | | llvm-svn: 122513
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-1/+2
| | | | llvm-svn: 121659
* a bunch of random cleanup, move a helper to CGT where it belongs.Chris Lattner2010-11-021-0/+4
| | | | llvm-svn: 118031
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-1/+3
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* Ignore NumberHack and give each SubRegIndex instance a unique enum value ↵Jakob Stoklund Olesen2010-05-251-1/+5
| | | | | | | | | | | instead. This passes lit tests, but I'll give it a go through the buildbots to smoke out any remaining places that depend on the old SubRegIndex numbering. Then I'll remove NumberHack entirely. llvm-svn: 104615
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-4/+14
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-1/+2
| | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. llvm-svn: 98934
* Finally change the instruction looking map to be a densemap fromChris Lattner2010-03-191-16/+11
| | | | | | | | | record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). llvm-svn: 98916
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-9/+9
| | | | | | Use CodeGenTarget::getInstNamespace in one place and fix it. llvm-svn: 98915
* revert 98912Chris Lattner2010-03-191-9/+9
| | | | llvm-svn: 98914
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-9/+9
| | | | llvm-svn: 98912
OpenPOWER on IntegriCloud