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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* Add the llvm.frameallocate and llvm.recoverframeallocation intrinsicsReid Kleckner2015-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | These intrinsics allow multiple functions to share a single stack allocation from one function's call frame. The function with the allocation may only perform one allocation, and it must be in the entry block. Functions accessing the allocation call llvm.recoverframeallocation with the function whose frame they are accessing and a frame pointer from an active call frame of that function. These intrinsics are very difficult to inline correctly, so the intention is that they be introduced rarely, or at least very late during EH preparation. Reviewers: echristo, andrew.w.kaylor Differential Revision: http://reviews.llvm.org/D6493 llvm-svn: 225746
* Masked Load/Store - Changed the order of parameters in intrinsics.Elena Demikhovsky2014-12-251-1/+2
| | | | | | | No functional changes. The documentation is coming. llvm-svn: 224829
* Use unique_ptr instead of DeleteContainerSeconds.Craig Topper2014-12-101-8/+7
| | | | llvm-svn: 223918
* Use range-based for loops. NFC.Craig Topper2014-12-091-9/+6
| | | | llvm-svn: 223762
* Masked Load / Store Intrinsics - the CodeGen part.Elena Demikhovsky2014-12-041-1/+2
| | | | | | | | | | | | | | | | | | I'm recommiting the codegen part of the patch. The vectorizer part will be send to review again. Masked Vector Load and Store Intrinsics. Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 223348
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-5/+4
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-9/+6
| | | | | | range-for isn't suitable. llvm-svn: 223260
* [Statepoints 2/4] Statepoint infrastructure for garbage collection: MI & ↵Philip Reames2014-12-011-0/+1
| | | | | | | | | | | | | | x86-64 Backend This is the second patch in a small series. This patch contains the MachineInstruction and x86-64 backend pieces required to lower Statepoints. It does not include the code to actually generate the STATEPOINT machine instruction and as a result, the entire patch is currently dead code. I will be submitting the SelectionDAG parts within the next 24-48 hours. Since those pieces are by far the most complicated, I wanted to minimize the size of that patch. That patch will include the tests which exercise the functionality in this patch. The entire series can be seen as one combined whole in http://reviews.llvm.org/D5683. The STATEPOINT psuedo node is generated after all gc values are explicitly spilled to stack slots. The purpose of this node is to wrap an actual call instruction while recording the spill locations of the meta arguments used for garbage collection and other purposes. The STATEPOINT is modeled as modifing all of those locations to prevent backend optimizations from forwarding the value from before the STATEPOINT to after the STATEPOINT. (Doing so would break relocation semantics for collectors which wish to relocate roots.) The implementation of STATEPOINT is closely modeled on PATCHPOINT. Eventually, much of the code in this patch will be removed. The long term plan is to merge the functionality provided by statepoints and patchpoints. Merging their implementations in the backend is likely to be a good starting point. Reviewed by: atrick, ributzka llvm-svn: 223085
* Revert "Masked Vector Load and Store Intrinsics."Duncan P. N. Exon Smith2014-11-281-2/+1
| | | | | | | | | | | This reverts commit r222632 (and follow-up r222636), which caused a host of LNT failures on an internal bot. I'll respond to the commit on the list with a reproduction of one of the failures. Conflicts: lib/Target/X86/X86TargetTransformInfo.cpp llvm-svn: 222936
* Use unique_ptr to simplify deletion.Craig Topper2014-11-281-5/+3
| | | | llvm-svn: 222929
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-231-1/+2
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-1/+2
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* TableGen: introduce support for MSBuiltinSaleem Abdulrasool2014-07-041-0/+2
| | | | | | | | | | | | | Add MSBuiltin which is similar in vein to GCCBuiltin. This allows for adding intrinsics for Microsoft compatibility to individual instructions. This is needed to permit the creation of ARM specific MSVC extensions. This is not currently in use, and requires an associated change in clang to enable use of the intrinsics defined by this new class. This merely sets the LLVM portion of the infrastructure in place to permit the use of this functionality. A separate set of changes will enable the new intrinsics. llvm-svn: 212350
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-4/+4
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-291-4/+7
| | | | | | No functionality change. llvm-svn: 205110
* Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)Tim Northover2014-03-281-4/+4
| | | | | | | | | | | | These are used in the ARM backends to aid type-checking on patterns involving intrinsics. By making sure one argument is an extended/truncated version of another. However, there's no reason to limit them to just vectors types. For example AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an intrinsic taking an i64 and returning an i32. llvm-svn: 205003
* Expose "noduplicate" attribute as a property for intrinsics.Eli Bendersky2014-03-181-0/+3
| | | | | | | | | | | | The "noduplicate" function attribute exists to prevent certain optimizations from duplicating calls to the function. This is important on platforms where certain function call duplications are unsafe (for example execution barriers for CUDA and OpenCL). This patch makes it possible to specify intrinsics as "noduplicate" and translates that to the appropriate function attribute. llvm-svn: 204200
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* clang-format a bit of code to make the next patch easier to read.Rafael Espindola2014-03-071-21/+5
| | | | llvm-svn: 203203
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-13/+4
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Delete all of the CodeGenInstructions from CodeGenTarget destructor.Craig Topper2014-02-061-0/+1
| | | | llvm-svn: 200906
* Fix a doxygen comment referencing the wrong method name.Craig Topper2014-02-051-2/+2
| | | | llvm-svn: 200825
* Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to ↵Craig Topper2014-01-241-2/+2
| | | | | | facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). llvm-svn: 200036
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-171-0/+40
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
* Lower stackmap intrinsics directly to their target opcode in the DAG builder.Andrew Trick2013-10-311-0/+2
| | | | llvm-svn: 193769
* Add v4f16 to supported value types.Pete Cooper2013-10-031-0/+1
| | | | | | This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion. llvm-svn: 191870
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-241-0/+3
| | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
* [Mips][msa] Value types for MSA support.Jack Carter2013-08-131-0/+1
| | | | | | | | | Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, and CodeGenTarget.cpp Patch by Daniel Sanders llvm-svn: 188326
* Add 'const' qualifier to some arrays.Craig Topper2013-07-151-1/+1
| | | | llvm-svn: 186312
* Extend 'readonly' and 'readnone' to work on function arguments as well asNick Lewycky2013-07-061-0/+6
| | | | | | | functions. Make the function attributes pass add it to known library functions and when it can deduce it. llvm-svn: 185735
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-171-1/+1
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64Elena Demikhovsky2012-12-241-0/+6
| | | | llvm-svn: 171026
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-3/+3
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-14/+15
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-191-0/+8
| | | | llvm-svn: 164261
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-111-6/+5
| | | | | | list of registers every time we want to look up a register by name. llvm-svn: 163659
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+2
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen2012-08-231-0/+9
| | | | | | | | | | | | Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. llvm-svn: 162460
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-1/+11
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* whitespaceAndrew Trick2012-07-071-3/+3
| | | | llvm-svn: 159890
* rdar://11542750 - llvm.trap should be marked no return.Chris Lattner2012-05-271-0/+3
| | | | llvm-svn: 157551
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-011-8/+0
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. llvm-svn: 151814
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-291-0/+8
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. llvm-svn: 151760
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-2/+2
| | | | llvm-svn: 149814
* Added MVT::v2f16Pete Cooper2012-01-121-0/+1
| | | | llvm-svn: 148067
* Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel2012-01-091-0/+20
| | | | | | | AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
* Add basic generic CodeGen support for half.Dan Gohman2011-12-201-0/+1
| | | | llvm-svn: 146927
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-0/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-1/+1
| | | | llvm-svn: 144747
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
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