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* [tablegen] Add locations to many PrintFatalError() callsDaniel Sanders2019-02-121-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: While working on the GISel Combiner, I noticed I was producing location-less error messages fairly often and set about fixing this. In the process, I noticed quite a few places elsewhere in TableGen that also neglected to include a relevant location. This patch adds locations to errors that relate to a specific record (or a field within it) and also have easy access to the relevant location. This is particularly useful when multiclasses are involved as many of these errors refer to the full name of a record and it's difficult to guess which substring is grep-able. Unfortunately, tablegen currently only supports Record granularity so it's not currently possible to point at a specific Init so these sometimes point at the record that caused the error rather than the precise origin of the error. Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, nhaehnle Reviewed By: nhaehnle Subscribers: jdoerfert, nhaehnle, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58077 llvm-svn: 353862
* [tblgen] Add a timer covering the time spent reading the Instruction defsDaniel Sanders2019-02-111-0/+4
| | | | | | | | | | | | | | | This patch adds a -time-regions option to tablegen that can enable timers (currently only one) that assess the performance of tablegen itself. This can be useful for identifying scaling problems with tablegen backends. This particular timer has allowed me to ignore time that is not attributed the GISel combiner pass. It's useful by itself but it is particularly useful in combination with https://reviews.llvm.org/D52954 which causes this period of time to be annotated within Xcode Instruments which in turn allows profile samples and recorded allocations attributed to reading instructions to be filtered out. llvm-svn: 353763
* [IR] Match intrinsic parameter by scalar/vectorwidthSimon Pilgrim2019-01-231-1/+1
| | | | | | | | | | | | | | This patch replaces the existing LLVMVectorSameWidth matcher with LLVMScalarOrSameVectorWidth. The matching args must be either scalars or vectors with the same number of elements, but in either case the scalar/element type can differ, specified by LLVMScalarOrSameVectorWidth. I've updated the _overflow intrinsics to demonstrate this - allowing it to return a i1 or <N x i1> overflow result, matching the scalar/vectorwidth of the other (add/sub/mul) result type. The masked load/store/gather/scatter intrinsics have also been updated to use this, although as we specify the reference type to be llvm_anyvector_ty we guarantee the mask will be <N x i1> so no change in behaviour Differential Revision: https://reviews.llvm.org/D57090 llvm-svn: 351957
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Mark @llvm.trap coldVedant Kumar2018-11-141-0/+3
| | | | | | | | | | | | | | | | A call to @llvm.trap can be expected to be cold (i.e. unlikely to be reached in a normal program execution). Outlining paths which unconditionally trap is an important memory saving. As the hot/cold splitting pass (imho) should not treat all noreturn calls as cold, explicitly mark @llvm.trap cold so that it can be outlined. Split out of https://reviews.llvm.org/D54244. Differential Revision: https://reviews.llvm.org/D54329 llvm-svn: 346885
* [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.Clement Courbet2018-10-251-1/+0
| | | | | | | | | | | | | | | | Summary: The pfm counters are now in the ExegesisTarget rather than the MCSchedModel (PR39165). This also compresses the pfm counter tables (PR37068). Reviewers: RKSimon, gchatelet Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D52932 llvm-svn: 345243
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-271-5/+5
| | | | | | | | | | | | Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
* [GlobalISel][Tablegen] Assign small opcodes to pseudosRoman Tereshin2018-05-231-7/+12
| | | | | | | | | | | | | | Sort pseudo instructions first while emitting enum's for target instructions info. That puts them close to each other and to generic G_* opcodes for GlobalISel. This makes it easier to build small jump tables over opcodes that could be directly embedded into MatchTable's Tablegen'erated for GlobalISel's InstructionSelect. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D47240 llvm-svn: 333135
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-061-11/+12
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
* TableGen: More helpful error messagesNicolai Haehnle2018-04-011-2/+6
| | | | | | | | | | | | | Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe Reviewers: arsenm, rampitec, b-sumner Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44936 Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92 llvm-svn: 328936
* Fix layering of CodeGen/TargetOpcodes.def by moving it to SupportDavid Blaikie2018-03-231-1/+1
| | | | | | | It's also used by utils/TableGen so needs to reside somewhere common to TableGen and CodeGen. llvm-svn: 328396
* [WebAssembly] Add except_ref as a first-class typeHeejin Ahn2018-03-081-0/+1
| | | | | | | | | | | | Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 llvm-svn: 326985
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [TableGen] Add a way of getting the number of generic opcodes without ↵Benjamin Kramer2018-01-241-4/+11
| | | | | | | | | | including modular CodeGen headers. This is a bit of a hack, but removes a cycle that broke modular builds of LLVM. Of course the cycle is still there in form of a dependency on the .def file. llvm-svn: 323383
* TableGen: Allow setting SDNodeProperties on intrinsicsMatt Arsenault2017-12-201-0/+7
| | | | | | | | | | | | | | | | | Allows preserving MachineMemOperands on intrinsics through selection. For reasons I don't understand, this is a static property of the pattern and the selector deliberately goes out of its way to drop if not present. Intrinsics already inherit from SDPatternOperator allowing them to be used directly in instruction patterns. SDPatternOperator has a list of SDNodeProperty, but you currently can't set them on the intrinsic. Without SDNPMemOperand, when the node is selected any memory operands are always dropped. Allowing setting this on the intrinsics avoids needing to introduce another equivalent target node just to have SDNPMemOperand set. llvm-svn: 321212
* Add MVT::v128i1, NFCKrzysztof Parzyszek2017-12-141-0/+1
| | | | | | | Hexagon HVX has type v128i8, comparing two vectors of that type will produce v128i1 types in SelectionDAG. llvm-svn: 320732
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-1/+1
| | | | | | namespace. NFC llvm-svn: 307362
* [MVT] add v1i1 MVTGuy Blank2017-05-181-0/+2
| | | | | | | | Adds the v1i1 MVT as a preparation for another commit (https://reviews.llvm.org/D32273) Differential Revision: https://reviews.llvm.org/D32540 llvm-svn: 303346
* TableGen: Add IntrHasSideEffects property for intrinsicsMatt Arsenault2017-04-281-0/+3
| | | | | | | | | | | | | | | The IntrNoMem, IntrReadMem, IntrWriteMem, and IntrArgMemOnly intrinsic properties differ from their corresponding LLVM IR attributes by specifying that the intrinsic, in addition to its memory properties, has no other side effects. The IntrHasSideEffects flag used in combination with one of the memory flags listed above, makes it possible to define an intrinsic such that its properties at the CodeGen layer match its properties at the IR layer. Patch by Tom Stellard llvm-svn: 301685
* Add speculatable function attributeMatt Arsenault2017-04-281-0/+3
| | | | | | | | This attribute tells the optimizer that the function may be speculated. Patch by Tom Stellard llvm-svn: 301680
* [MVT][SVE] Scalable vector MVTs (2/3)Amara Emerson2017-04-201-0/+39
| | | | | | | | | | | Adds scalable vector machine value types, and updates the switch statements required for tablegen. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32018 llvm-svn: 300840
* [tablegen] Use categories on options that only matter to one emitter.Daniel Sanders2017-03-271-4/+9
| | | | | | | | | | | | | | | | Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-2/+2
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Add IntrInaccessibleMemOnly property for intrinsicsAndrew Kaylor2016-11-221-1/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D26485 llvm-svn: 287680
* Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-091-0/+10
| | | | | | | | | represents a relocatable immediate.", with a fix for 32-bit x86. Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions that take a global address operand. llvm-svn: 286420
* Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-091-10/+0
| | | | | | | | | represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
* X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable ↵Peter Collingbourne2016-11-091-0/+10
| | | | | | | | | | | | | | | immediate. A relocatable immediate is either an immediate operand or an operand that can be relocated by the linker to an immediate, such as a regular symbol in non-PIC code. Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands of type "imm32_su". Remove a number of now-redundant patterns. Differential Revision: https://reviews.llvm.org/D25812 llvm-svn: 286384
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-031-2/+1
| | | | | | | | 2 new intrinsics covering AVX-512 compress/expand functionality. This implementation includes syntax, DAG builder, operation lowering and tests. Does not include: handling of illegal data types, codegen prepare pass and the cost model. llvm-svn: 285876
* GlobalISel: Remove explicit enumerator values from .def file.Tim Northover2016-07-201-1/+1
| | | | | | | | | | They were all auto-incremented from 0 anyway, and I'm getting really annoying conflicts and runtime failures when different people add more for GlobalISel (and even when I'm refactoring my own patches). NFC. llvm-svn: 276204
* IR: Sort generic intrinsics before target specific onesJustin Bogner2016-07-151-9/+15
| | | | | | | | | | | | This splits out the intrinsic table such that generic intrinsics come first and target specific intrinsics are grouped by target. From here we can find out which target an intrinsic is for or differentiate between generic and target intrinsics. The motivation here is to make it easier to move target specific intrinsic handling out of generic code. llvm-svn: 275575
* TableGen: Fix a confusing use of both i and I as variables. NFCJustin Bogner2016-07-141-5/+5
| | | | llvm-svn: 275450
* Add a 'Returned' intrinsic property corresponding to the 'returned' argument ↵Hal Finkel2016-07-111-0/+3
| | | | | | | | | | attribute This will be used by the upcoming llvm.noalias intrinsic. Differential Revision: http://reviews.llvm.org/D22201 llvm-svn: 275034
* Add writeonly IR attributeNicolai Haehnle2016-07-041-0/+3
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* TableGen: Use StringRef instead of std::stringMatt Arsenault2016-05-251-2/+2
| | | | llvm-svn: 270741
* Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle2016-04-211-8/+4
| | | | | | | | | | | | | | | | | | Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
* Add IntrWrite[Arg]Mem intrinsic propertyNicolai Haehnle2016-04-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | Summary: This property is used to mark an intrinsic that only writes to memory, but neither reads from memory nor has other side effects. An example where this is useful is the llvm.amdgcn.buffer.store.format.* intrinsic, which corresponds to a store instruction that goes through a special buffer descriptor rather than through a plain pointer. With this property, the intrinsic should still be handled as having side effects at the LLVM IR level, but machine scheduling can make smarter decisions. Reviewers: tstellarAMD, arsenm, joker.eph, reames Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18291 llvm-svn: 266826
* Minor code cleanup. NFC.Junmo Park2016-04-121-2/+2
| | | | llvm-svn: 266045
* SelectionDAG: Make Properties a field of SDPatternOperatorMatt Arsenault2016-02-101-1/+1
| | | | | | | | | Currently you can't specify node properties like commutativity on a PatFrag. If you want to create a PatFrag on a commutative node with a hasOneUse predicate, this enables you to specify that the PatFrag is also commutable. llvm-svn: 260404
* Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs array inDavid L Kreitzer2016-02-031-12/+2
| | | | | | | | CodeGenTarget.cpp to avoid the ordering dependence. NFCI. Differential Revision: http://reviews.llvm.org/D16826 llvm-svn: 259726
* Minor performance tweaks to llvm-tblgen (and a few that might be a good idea)Reid Kleckner2016-02-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a reserve call to an expensive function (`llvm::LoadIntrinsics`), and may fix a few other low hanging performance fruit (I've put them in comments for now, so we can discuss). **Motivation:** As I'm sure other developers do, when I build LLVM, I build the entire project with the same config (`Debug`, `MinSizeRel`, `Release`, or `RelWithDebInfo`). However, the `Debug` config also builds llvm-tblgen in `Debug` mode. Later build steps that run llvm-tblgen then can actually be the slowest steps in the entire build. Nobody likes slow builds. Reviewers: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D16832 Patch by Alexander G. Riccio llvm-svn: 259683
* Sort intrinsics by LLVM intrinsic name, rather than tablegen def nameReid Kleckner2016-01-261-0/+4
| | | | | | | | | | | | Step one towards using a simple binary search to lookup intrinsic IDs instead of our crazy table generated switch+memcmp+startswith code that makes Function.cpp take about a minute to compile. See PR24785 and PR11951 for why we should do this. The X86 backend contains tables that need to be sorted on intrinsic ID, so reorder those. llvm-svn: 258757
* [GlobalISel] Add a generic machine opcode for ADD.Quentin Colombet2016-01-201-0/+5
| | | | | | | | | | | The selection process being split into separate passes, we need generic opcodes to translate the LLVM IR to target independent code. This patch adds an opcode for addition: G_ADD. Differential Revision: http://reviews.llvm.org/D15472 llvm-svn: 258333
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-1/+1
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* Add names for the new vector types in CodeGenTarget.cppKrzysztof Parzyszek2015-11-241-0/+9
| | | | llvm-svn: 253989
* Revert change that accidentally snuck into r253955.Craig Topper2015-11-241-2/+1
| | | | llvm-svn: 253956
* [TableGen] Use array_pod_sort. NFCCraig Topper2015-11-241-2/+3
| | | | llvm-svn: 253955
* [TableGen] Allow TokenTy in intrinsic signaturesJoseph Tremoulet2015-09-021-0/+1
| | | | | | | | | | | | | | | | | Summary: Add the necessary plumbing so that llvm_token_ty can be used as an argument/return type in intrinsic definitions and correspondingly require TokenTy in function types. TokenTy is an opaque type that has no target lowering, but can be used in machine-independent intrinsics. It is required for the upcoming llvm.eh.padparam intrinsic. Reviewers: majnemer, rnk Subscribers: stoklund, llvm-commits Differential Revision: http://reviews.llvm.org/D12532 llvm-svn: 246651
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