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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-1/+7
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | llvm-svn: 44969
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* Add sqrt and powi intrinsics for long double.Dale Johannesen2007-09-281-0/+2
| | | | llvm-svn: 42423
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+1
| | | | | | between two registers in the specific class. llvm-svn: 42123
* Add MVT::fAny for overloading intrinsics on floating-point types.Dan Gohman2007-08-161-1/+3
| | | | llvm-svn: 41128
* This is the patch to provide clean intrinsic function overloading support in ↵Chandler Carruth2007-08-041-3/+2
| | | | | | | | LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported. llvm-svn: 40807
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-1/+15
| | | | | | MBB's. PR1350 llvm-svn: 40518
* Teach TableGen about the new vector types.Christopher Lamb2007-07-261-0/+4
| | | | llvm-svn: 40513
* No need for noResults anymore.Evan Cheng2007-07-201-1/+0
| | | | llvm-svn: 40075
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-1/+13
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Eliminate an unused parameter.Dan Gohman2007-07-131-2/+2
| | | | llvm-svn: 39828
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-101-3/+4
| | | | llvm-svn: 38498
* ImmutablePredicateOperand is no more.Evan Cheng2007-07-061-2/+1
| | | | llvm-svn: 37963
* Instructions with ImmutablePredicateOperand aren't really predicable since ↵Evan Cheng2007-07-051-1/+4
| | | | | | their predicates are fixed at isel time. llvm-svn: 37899
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add support to tablegen for specifying subregister classes on a per register ↵Christopher Lamb2007-06-131-0/+10
| | | | | | class basis. llvm-svn: 37572
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-061-0/+1
| | | | | | are used to predicate instructions. llvm-svn: 37465
* Remove the operator<< for MVT::ValueType in preparation for MVT::ValueTypeDan Gohman2007-06-041-5/+0
| | | | | | | being changed from an enum to an integer type, which can't have a custom operator<< overload. llvm-svn: 37412
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-2/+2
| | | | | | without having a PredicateOperand. llvm-svn: 37116
* For PR1297:Reid Spencer2007-04-011-3/+7
| | | | | | | | | | Implement code generation for overloaded intrinsic functions. The basic difference is that "actual" argument types must be provided when constructing intrinsic names and types. Also, for recognition, only the prefix is examined. If it matches, the suffix is assumed to match. The suffix is checked by the Verifier, however. llvm-svn: 35539
* Add support for the v1i64 type. This makes better code for this:Bill Wendling2007-03-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #include <mmintrin.h> extern __m64 C; void baz(__v2si *A, __v2si *B) { *A = C; _mm_empty(); } We get this: _baz: call "L1$pb" "L1$pb": popl %eax movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax movq (%eax), %mm0 movl 4(%esp), %eax movq %mm0, (%eax) emms ret GCC gives us this: _baz: pushl %ebx call L3 "L00000000001$pb": L3: popl %ebx subl $8, %esp movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax movl (%eax), %edx movl 4(%eax), %ecx movl 16(%esp), %eax movl %edx, (%eax) movl %ecx, 4(%eax) emms addl $8, %esp popl %ebx ret llvm-svn: 35351
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35159
* reapplyChris Lattner2007-02-271-6/+2
| | | | llvm-svn: 34697
* Backing outEvan Cheng2007-02-271-2/+6
| | | | | | | | | | CodeGenTarget.cpp updated: 1.82 -> 1.83 Record.cpp updated: 1.55 -> 1.56 Record.h updated: 1.59 -> 1.60 TableGen.cpp updated: 1.47 -> 1.48 It's missing CallingConvEmitter.h llvm-svn: 34693
* initial support for calling convention generation, still unfinished.Chris Lattner2007-02-271-6/+2
| | | | llvm-svn: 34682
* Files missing from LABEL check in.Jim Laskey2007-01-261-1/+8
| | | | llvm-svn: 33539
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-2/+3
| | | | llvm-svn: 32333
* Match TargetInstrInfo changes.Evan Cheng2006-12-011-3/+2
| | | | llvm-svn: 32107
* Remove the isTwoAddress property from the CodeGenInstruction class. It shouldChris Lattner2006-11-151-1/+17
| | | | | | | | | | not be used for anything other than backwards compat constraint handling. Add support for a new DisableEncoding property which contains a list of registers that should not be encoded by the generated code emitter. Convert the codeemitter generator to use this, fixing some PPC JIT regressions. llvm-svn: 31769
* ADd support for adding constraints to suboperandsChris Lattner2006-11-151-29/+92
| | | | llvm-svn: 31748
* allow ptr_rc to explicitly appear in an instructions operand list, it doesn'tChris Lattner2006-11-101-1/+2
| | | | | | have to be a subpart of a complex operand. llvm-svn: 31618
* emit TIED_TO correctlyChris Lattner2006-11-071-2/+2
| | | | llvm-svn: 31484
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-21/+30
| | | | | | to extend. llvm-svn: 31481
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-061-0/+2
| | | | llvm-svn: 31480
* Clean up some code.Evan Cheng2006-11-041-1/+3
| | | | llvm-svn: 31451
* eliminate need for the NumMIOperands field in Operand.Chris Lattner2006-11-031-1/+13
| | | | llvm-svn: 31432
* Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else ↵Evan Cheng2006-11-011-0/+3
| | | | | | throw an exception. llvm-svn: 31361
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-0/+48
| | | | llvm-svn: 31333
* Added properties such as SDNPHasChain to ComplexPattern.Evan Cheng2006-10-111-0/+14
| | | | llvm-svn: 30890
* Allow more use of iPTR in patterns.Evan Cheng2006-06-151-22/+22
| | | | llvm-svn: 28790
* Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.Evan Cheng2006-05-181-3/+0
| | | | llvm-svn: 28376
* TypoEvan Cheng2006-05-171-2/+2
| | | | llvm-svn: 28366
* Remove PointerType from target definition. Use abstract type MVT::iPTR toEvan Cheng2006-05-171-31/+27
| | | | | | represent pointer type. llvm-svn: 28363
* Allow patterns to refer to physical registers that belong to multipleEvan Cheng2006-05-161-0/+17
| | | | | | register classes. llvm-svn: 28323
* Fix a typo: Instr* -> Intr*Chris Lattner2006-04-101-3/+3
| | | | llvm-svn: 27568
* Only compute intrinsic valuetypes when in a target .td file.Chris Lattner2006-03-281-2/+12
| | | | llvm-svn: 27197
* revert this, it breaks things.Chris Lattner2006-03-281-4/+3
| | | | llvm-svn: 27196
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