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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* [TableGen] Use StringRef instead of std::string for CodeGenInstruction ↵Craig Topper2017-07-071-1/+1
| | | | | | namespace. NFC llvm-svn: 307362
* [MVT] add v1i1 MVTGuy Blank2017-05-181-0/+2
| | | | | | | | Adds the v1i1 MVT as a preparation for another commit (https://reviews.llvm.org/D32273) Differential Revision: https://reviews.llvm.org/D32540 llvm-svn: 303346
* TableGen: Add IntrHasSideEffects property for intrinsicsMatt Arsenault2017-04-281-0/+3
| | | | | | | | | | | | | | | The IntrNoMem, IntrReadMem, IntrWriteMem, and IntrArgMemOnly intrinsic properties differ from their corresponding LLVM IR attributes by specifying that the intrinsic, in addition to its memory properties, has no other side effects. The IntrHasSideEffects flag used in combination with one of the memory flags listed above, makes it possible to define an intrinsic such that its properties at the CodeGen layer match its properties at the IR layer. Patch by Tom Stellard llvm-svn: 301685
* Add speculatable function attributeMatt Arsenault2017-04-281-0/+3
| | | | | | | | This attribute tells the optimizer that the function may be speculated. Patch by Tom Stellard llvm-svn: 301680
* [MVT][SVE] Scalable vector MVTs (2/3)Amara Emerson2017-04-201-0/+39
| | | | | | | | | | | Adds scalable vector machine value types, and updates the switch statements required for tablegen. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32018 llvm-svn: 300840
* [tablegen] Use categories on options that only matter to one emitter.Daniel Sanders2017-03-271-4/+9
| | | | | | | | | | | | | | | | Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-2/+2
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Add IntrInaccessibleMemOnly property for intrinsicsAndrew Kaylor2016-11-221-1/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D26485 llvm-svn: 287680
* Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-091-0/+10
| | | | | | | | | represents a relocatable immediate.", with a fix for 32-bit x86. Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions that take a global address operand. llvm-svn: 286420
* Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-091-10/+0
| | | | | | | | | represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
* X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable ↵Peter Collingbourne2016-11-091-0/+10
| | | | | | | | | | | | | | | immediate. A relocatable immediate is either an immediate operand or an operand that can be relocated by the linker to an immediate, such as a regular symbol in non-PIC code. Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands of type "imm32_su". Remove a number of now-redundant patterns. Differential Revision: https://reviews.llvm.org/D25812 llvm-svn: 286384
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-031-2/+1
| | | | | | | | 2 new intrinsics covering AVX-512 compress/expand functionality. This implementation includes syntax, DAG builder, operation lowering and tests. Does not include: handling of illegal data types, codegen prepare pass and the cost model. llvm-svn: 285876
* GlobalISel: Remove explicit enumerator values from .def file.Tim Northover2016-07-201-1/+1
| | | | | | | | | | They were all auto-incremented from 0 anyway, and I'm getting really annoying conflicts and runtime failures when different people add more for GlobalISel (and even when I'm refactoring my own patches). NFC. llvm-svn: 276204
* IR: Sort generic intrinsics before target specific onesJustin Bogner2016-07-151-9/+15
| | | | | | | | | | | | This splits out the intrinsic table such that generic intrinsics come first and target specific intrinsics are grouped by target. From here we can find out which target an intrinsic is for or differentiate between generic and target intrinsics. The motivation here is to make it easier to move target specific intrinsic handling out of generic code. llvm-svn: 275575
* TableGen: Fix a confusing use of both i and I as variables. NFCJustin Bogner2016-07-141-5/+5
| | | | llvm-svn: 275450
* Add a 'Returned' intrinsic property corresponding to the 'returned' argument ↵Hal Finkel2016-07-111-0/+3
| | | | | | | | | | attribute This will be used by the upcoming llvm.noalias intrinsic. Differential Revision: http://reviews.llvm.org/D22201 llvm-svn: 275034
* Add writeonly IR attributeNicolai Haehnle2016-07-041-0/+3
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* TableGen: Use StringRef instead of std::stringMatt Arsenault2016-05-251-2/+2
| | | | llvm-svn: 270741
* Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle2016-04-211-8/+4
| | | | | | | | | | | | | | | | | | Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
* Add IntrWrite[Arg]Mem intrinsic propertyNicolai Haehnle2016-04-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | Summary: This property is used to mark an intrinsic that only writes to memory, but neither reads from memory nor has other side effects. An example where this is useful is the llvm.amdgcn.buffer.store.format.* intrinsic, which corresponds to a store instruction that goes through a special buffer descriptor rather than through a plain pointer. With this property, the intrinsic should still be handled as having side effects at the LLVM IR level, but machine scheduling can make smarter decisions. Reviewers: tstellarAMD, arsenm, joker.eph, reames Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18291 llvm-svn: 266826
* Minor code cleanup. NFC.Junmo Park2016-04-121-2/+2
| | | | llvm-svn: 266045
* SelectionDAG: Make Properties a field of SDPatternOperatorMatt Arsenault2016-02-101-1/+1
| | | | | | | | | Currently you can't specify node properties like commutativity on a PatFrag. If you want to create a PatFrag on a commutative node with a hasOneUse predicate, this enables you to specify that the PatFrag is also commutable. llvm-svn: 260404
* Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs array inDavid L Kreitzer2016-02-031-12/+2
| | | | | | | | CodeGenTarget.cpp to avoid the ordering dependence. NFCI. Differential Revision: http://reviews.llvm.org/D16826 llvm-svn: 259726
* Minor performance tweaks to llvm-tblgen (and a few that might be a good idea)Reid Kleckner2016-02-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a reserve call to an expensive function (`llvm::LoadIntrinsics`), and may fix a few other low hanging performance fruit (I've put them in comments for now, so we can discuss). **Motivation:** As I'm sure other developers do, when I build LLVM, I build the entire project with the same config (`Debug`, `MinSizeRel`, `Release`, or `RelWithDebInfo`). However, the `Debug` config also builds llvm-tblgen in `Debug` mode. Later build steps that run llvm-tblgen then can actually be the slowest steps in the entire build. Nobody likes slow builds. Reviewers: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D16832 Patch by Alexander G. Riccio llvm-svn: 259683
* Sort intrinsics by LLVM intrinsic name, rather than tablegen def nameReid Kleckner2016-01-261-0/+4
| | | | | | | | | | | | Step one towards using a simple binary search to lookup intrinsic IDs instead of our crazy table generated switch+memcmp+startswith code that makes Function.cpp take about a minute to compile. See PR24785 and PR11951 for why we should do this. The X86 backend contains tables that need to be sorted on intrinsic ID, so reorder those. llvm-svn: 258757
* [GlobalISel] Add a generic machine opcode for ADD.Quentin Colombet2016-01-201-0/+5
| | | | | | | | | | | The selection process being split into separate passes, we need generic opcodes to translate the LLVM IR to target independent code. This patch adds an opcode for addition: G_ADD. Differential Revision: http://reviews.llvm.org/D15472 llvm-svn: 258333
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-1/+1
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* Add names for the new vector types in CodeGenTarget.cppKrzysztof Parzyszek2015-11-241-0/+9
| | | | llvm-svn: 253989
* Revert change that accidentally snuck into r253955.Craig Topper2015-11-241-2/+1
| | | | llvm-svn: 253956
* [TableGen] Use array_pod_sort. NFCCraig Topper2015-11-241-2/+3
| | | | llvm-svn: 253955
* [TableGen] Allow TokenTy in intrinsic signaturesJoseph Tremoulet2015-09-021-0/+1
| | | | | | | | | | | | | | | | | Summary: Add the necessary plumbing so that llvm_token_ty can be used as an argument/return type in intrinsic definitions and correspondingly require TokenTy in function types. TokenTy is an opaque type that has no target lowering, but can be used in machine-independent intrinsics. It is required for the upcoming llvm.eh.padparam intrinsic. Reviewers: majnemer, rnk Subscribers: stoklund, llvm-commits Differential Revision: http://reviews.llvm.org/D12532 llvm-svn: 246651
* Rename llvm.frameescape and llvm.framerecover to localescape and localrecoverReid Kleckner2015-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Initially, these intrinsics seemed like part of a family of "frame" related intrinsics, but now I think that's more confusing than helpful. Initially, the LangRef specified that this would create a new kind of allocation that would be allocated at a fixed offset from the frame pointer (EBP/RBP). We ended up dropping that design, and leaving the stack frame layout alone. These intrinsics are really about sharing local stack allocations, not frame pointers. I intend to go further and add an `llvm.localaddress()` intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being used to address locals, which should not be confused with the frame pointer. Naming suggestions at this point are welcome, I'm happy to re-run sed. Reviewers: majnemer, nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11011 llvm-svn: 241633
* [CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.Sanjoy Das2015-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This instruction encodes a loading operation that may fault, and a label to branch to if the load page-faults. The locations of potentially faulting loads and their "handler" destinations are recorded in a FaultMap section, meant to be consumed by LLVM's clients. Nothing generates FAULTING_LOAD_OP instructions yet, but they will be used in a future change. The documentation (FaultMaps.rst) needs improvement and I will update this diff with a more expanded version shortly. Depends on D10196 Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin Reviewed By: atrick, pgavlin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10197 llvm-svn: 239740
* [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper2015-06-021-3/+3
| | | | llvm-svn: 238806
* Add initial support for the convergent attribute.Owen Anderson2015-05-261-0/+3
| | | | llvm-svn: 238264
* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-111-3/+3
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* Add support for v1i128 type.Kit Barton2015-04-171-0/+1
| | | | | | | | | | | | The v1i128 type is needed for the quadword add/substract instructions introduced in POWER8. Futhermore, the PowerPC ABI specifies that parameters of type v1i128 are to be passed in a single vector register, while parameters of type i128 are passed in pairs of GPRs. Thus, it is necessary to be able to differentiate between v1i128 and i128 in LLVM. http://reviews.llvm.org/D8564 llvm-svn: 235198
* Intrinsics: introduce llvm_any_ty aka ValueType AnyRamkumar Ramachandra2015-01-221-0/+1
| | | | | | | | | | | | | | | Specifically, gc.result benefits from this greatly. Instead of: gc.result.int.* gc.result.float.* gc.result.ptr.* ... We now have a gc.result.* that can specialize to literally any type. Differential Revision: http://reviews.llvm.org/D7020 llvm-svn: 226857
* Add the llvm.frameallocate and llvm.recoverframeallocation intrinsicsReid Kleckner2015-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | These intrinsics allow multiple functions to share a single stack allocation from one function's call frame. The function with the allocation may only perform one allocation, and it must be in the entry block. Functions accessing the allocation call llvm.recoverframeallocation with the function whose frame they are accessing and a frame pointer from an active call frame of that function. These intrinsics are very difficult to inline correctly, so the intention is that they be introduced rarely, or at least very late during EH preparation. Reviewers: echristo, andrew.w.kaylor Differential Revision: http://reviews.llvm.org/D6493 llvm-svn: 225746
* Masked Load/Store - Changed the order of parameters in intrinsics.Elena Demikhovsky2014-12-251-1/+2
| | | | | | | No functional changes. The documentation is coming. llvm-svn: 224829
* Use unique_ptr instead of DeleteContainerSeconds.Craig Topper2014-12-101-8/+7
| | | | llvm-svn: 223918
* Use range-based for loops. NFC.Craig Topper2014-12-091-9/+6
| | | | llvm-svn: 223762
* Masked Load / Store Intrinsics - the CodeGen part.Elena Demikhovsky2014-12-041-1/+2
| | | | | | | | | | | | | | | | | | I'm recommiting the codegen part of the patch. The vectorizer part will be send to review again. Masked Vector Load and Store Intrinsics. Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 223348
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-5/+4
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-9/+6
| | | | | | range-for isn't suitable. llvm-svn: 223260
* [Statepoints 2/4] Statepoint infrastructure for garbage collection: MI & ↵Philip Reames2014-12-011-0/+1
| | | | | | | | | | | | | | x86-64 Backend This is the second patch in a small series. This patch contains the MachineInstruction and x86-64 backend pieces required to lower Statepoints. It does not include the code to actually generate the STATEPOINT machine instruction and as a result, the entire patch is currently dead code. I will be submitting the SelectionDAG parts within the next 24-48 hours. Since those pieces are by far the most complicated, I wanted to minimize the size of that patch. That patch will include the tests which exercise the functionality in this patch. The entire series can be seen as one combined whole in http://reviews.llvm.org/D5683. The STATEPOINT psuedo node is generated after all gc values are explicitly spilled to stack slots. The purpose of this node is to wrap an actual call instruction while recording the spill locations of the meta arguments used for garbage collection and other purposes. The STATEPOINT is modeled as modifing all of those locations to prevent backend optimizations from forwarding the value from before the STATEPOINT to after the STATEPOINT. (Doing so would break relocation semantics for collectors which wish to relocate roots.) The implementation of STATEPOINT is closely modeled on PATCHPOINT. Eventually, much of the code in this patch will be removed. The long term plan is to merge the functionality provided by statepoints and patchpoints. Merging their implementations in the backend is likely to be a good starting point. Reviewed by: atrick, ributzka llvm-svn: 223085
* Revert "Masked Vector Load and Store Intrinsics."Duncan P. N. Exon Smith2014-11-281-2/+1
| | | | | | | | | | | This reverts commit r222632 (and follow-up r222636), which caused a host of LNT failures on an internal bot. I'll respond to the commit on the list with a reproduction of one of the failures. Conflicts: lib/Target/X86/X86TargetTransformInfo.cpp llvm-svn: 222936
* Use unique_ptr to simplify deletion.Craig Topper2014-11-281-5/+3
| | | | llvm-svn: 222929
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-231-1/+2
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-1/+2
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
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