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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* spell this variable rightChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23095
* Expose a new flag to TargetInstrInfoChris Lattner2005-08-261-0/+1
| | | | llvm-svn: 23094
* Split register class "Methods" into MethodProtos and MethodBodiesChris Lattner2005-08-191-4/+10
| | | | llvm-svn: 22928
* Read the namespace field from register classesChris Lattner2005-08-191-0/+7
| | | | llvm-svn: 22918
* Fix a problem jeffc noticedChris Lattner2005-08-191-0/+1
| | | | llvm-svn: 22903
* Figure out how many operands each instruction has, keep track of whetherChris Lattner2005-08-181-4/+7
| | | | | | or not it's variable. llvm-svn: 22885
* Remove trailing whitespaceMisha Brukman2005-04-221-5/+5
| | | | llvm-svn: 21428
* Refactor code for numbering instructions into CodeGenTarget.Chris Lattner2005-01-221-0/+16
| | | | llvm-svn: 19758
* Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.Chris Lattner2005-01-021-0/+2
| | | | llvm-svn: 19243
* * Add option to read isLittleEndianEncoding for InstrInfo classesMisha Brukman2004-10-141-0/+9
| | | | | | * Doxygen-ify some function comments llvm-svn: 16974
* Add initial support for variants. This just parses the new format, noChris Lattner2004-10-031-1/+12
| | | | | | functionality is added llvm-svn: 16636
* Add support for the isLoad and isStore flags, needed by the instruction ↵Nate Begeman2004-09-281-0/+2
| | | | | | scheduler llvm-svn: 16554
* Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAGChris Lattner2004-09-281-0/+1
| | | | llvm-svn: 16553
* Alignment is now in bits.Chris Lattner2004-08-211-2/+1
| | | | llvm-svn: 15976
* Make alignment be in bits, just like size isChris Lattner2004-08-211-1/+2
| | | | llvm-svn: 15969
* Support "Methods" in register classes in CodgeGenRegisterClassChris Lattner2004-08-211-0/+6
| | | | llvm-svn: 15965
* Start parsing register classes into a more structured formChris Lattner2004-08-211-0/+32
| | | | llvm-svn: 15961
* Read in declared reg sizesChris Lattner2004-08-211-0/+5
| | | | llvm-svn: 15960
* Use CodeGenRegister class to make reading in of register information moreChris Lattner2004-08-161-1/+14
| | | | | | systematic. llvm-svn: 15805
* Make the AsmWriter a first-class tblgen object. Allow targets to specifyChris Lattner2004-08-141-4/+17
| | | | | | name of the generated asmwriter class, and the name of the format string. llvm-svn: 15747
* Start parsing more information from the Operand informationChris Lattner2004-08-111-3/+10
| | | | llvm-svn: 15644
* Remove special case hacksChris Lattner2004-08-111-8/+2
| | | | llvm-svn: 15643
* Parse the operand list of the instruction. We currently support register ↵Chris Lattner2004-08-011-5/+36
| | | | | | and immediate operands. llvm-svn: 15390
* Initial cut at an asm writer emitter. So far, this only handles emission ofChris Lattner2004-08-011-2/+11
| | | | | | instructions, and only instructions that take no operands at that! llvm-svn: 15386
* Add, and start using, the CodeGenInstruction class. This class representsChris Lattner2004-08-011-0/+36
| | | | | | an instance of the Instruction tablegen class. llvm-svn: 15385
* Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)Chris Lattner2004-08-011-0/+99
llvm-svn: 15382
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