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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-2/+9
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Reapply 63765. Patches for clang and llvm-gcc to follow.Dale Johannesen2009-02-051-3/+7
| | | | llvm-svn: 63812
* Reverting 63765. This broke the build of both clangDale Johannesen2009-02-041-7/+3
| | | | | | and llvm-gcc. llvm-svn: 63786
* New feature: add support for target intrinsics being defined in theNate Begeman2009-02-041-3/+7
| | | | | | | | | target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. llvm-svn: 63765
* add nocapture attribute to llvm.mem* intrinsics and have tblgenChris Lattner2009-01-121-1/+4
| | | | | | parse them. tblgen doesn't yet do anything with this info though. llvm-svn: 62065
* Improve support for type-generic vector intrinsics by teaching TableGen howBob Wilson2009-01-071-2/+26
| | | | | | | | to handle LLVMMatchType intrinsic parameters, and by adding new subclasses of LLVMMatchType to match vector types with integral elements that are either twice as wide or half as wide as the elements of the matched type. llvm-svn: 61834
* Added support for vector widening.Mon P Wang2008-12-181-0/+6
| | | | llvm-svn: 61209
* Modify the intrinsics pattern to separate out the "return" types from theBill Wendling2008-11-131-16/+29
| | | | | | | | | | "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; llvm-svn: 59237
* Factor the code for determining the target-specific instructionDan Gohman2008-08-201-0/+15
| | | | | | namespace out of the isel emitters and into common code. llvm-svn: 55079
* Fix the string for MVT::isVoid.Dan Gohman2008-08-201-1/+1
| | | | llvm-svn: 55034
* Added support for overloading intrinsics (atomics) based on pointersMon P Wang2008-07-301-1/+3
| | | | | | | to different address spaces. This alters the naming scheme for those intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32 llvm-svn: 54195
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-5/+17
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-0/+2
| | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub llvm-svn: 52706
* - Add "Commutative" property to intrinsics. This allows tblgen to generate ↵Evan Cheng2008-06-161-0/+3
| | | | | | | | the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. llvm-svn: 52353
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-9/+9
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman2008-04-031-10/+2
| | | | | | | | | | | | CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. llvm-svn: 49123
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-1/+8
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-1/+8
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+6
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb2008-01-311-0/+12
| | | | | | | | | | complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. llvm-svn: 46606
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-0/+6
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-061-264/+2
| | | | | | getName() accessor. llvm-svn: 45645
* change getQualifiedName to be a global function.Chris Lattner2008-01-051-0/+11
| | | | | | | | Split the pattern parsing code out from the dag isel emitter into it's own file. No functionality change. llvm-svn: 45632
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-1/+7
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | llvm-svn: 44969
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* Add sqrt and powi intrinsics for long double.Dale Johannesen2007-09-281-0/+2
| | | | llvm-svn: 42423
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+1
| | | | | | between two registers in the specific class. llvm-svn: 42123
* Add MVT::fAny for overloading intrinsics on floating-point types.Dan Gohman2007-08-161-1/+3
| | | | llvm-svn: 41128
* This is the patch to provide clean intrinsic function overloading support in ↵Chandler Carruth2007-08-041-3/+2
| | | | | | | | LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported. llvm-svn: 40807
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-1/+15
| | | | | | MBB's. PR1350 llvm-svn: 40518
* Teach TableGen about the new vector types.Christopher Lamb2007-07-261-0/+4
| | | | llvm-svn: 40513
* No need for noResults anymore.Evan Cheng2007-07-201-1/+0
| | | | llvm-svn: 40075
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-1/+13
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Eliminate an unused parameter.Dan Gohman2007-07-131-2/+2
| | | | llvm-svn: 39828
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-101-3/+4
| | | | llvm-svn: 38498
* ImmutablePredicateOperand is no more.Evan Cheng2007-07-061-2/+1
| | | | llvm-svn: 37963
* Instructions with ImmutablePredicateOperand aren't really predicable since ↵Evan Cheng2007-07-051-1/+4
| | | | | | their predicates are fixed at isel time. llvm-svn: 37899
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add support to tablegen for specifying subregister classes on a per register ↵Christopher Lamb2007-06-131-0/+10
| | | | | | class basis. llvm-svn: 37572
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-061-0/+1
| | | | | | are used to predicate instructions. llvm-svn: 37465
* Remove the operator<< for MVT::ValueType in preparation for MVT::ValueTypeDan Gohman2007-06-041-5/+0
| | | | | | | being changed from an enum to an integer type, which can't have a custom operator<< overload. llvm-svn: 37412
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-2/+2
| | | | | | without having a PredicateOperand. llvm-svn: 37116
* For PR1297:Reid Spencer2007-04-011-3/+7
| | | | | | | | | | Implement code generation for overloaded intrinsic functions. The basic difference is that "actual" argument types must be provided when constructing intrinsic names and types. Also, for recognition, only the prefix is examined. If it matches, the suffix is assumed to match. The suffix is checked by the Verifier, however. llvm-svn: 35539
* Add support for the v1i64 type. This makes better code for this:Bill Wendling2007-03-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #include <mmintrin.h> extern __m64 C; void baz(__v2si *A, __v2si *B) { *A = C; _mm_empty(); } We get this: _baz: call "L1$pb" "L1$pb": popl %eax movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax movq (%eax), %mm0 movl 4(%esp), %eax movq %mm0, (%eax) emms ret GCC gives us this: _baz: pushl %ebx call L3 "L00000000001$pb": L3: popl %ebx subl $8, %esp movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax movl (%eax), %edx movl 4(%eax), %ecx movl 16(%esp), %eax movl %edx, (%eax) movl %ecx, 4(%eax) emms addl $8, %esp popl %ebx ret llvm-svn: 35351
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35159
* reapplyChris Lattner2007-02-271-6/+2
| | | | llvm-svn: 34697
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