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path: root/llvm/utils/TableGen/CodeGenTarget.cpp
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* Lower stackmap intrinsics directly to their target opcode in the DAG builder.Andrew Trick2013-10-311-0/+2
| | | | llvm-svn: 193769
* Add v4f16 to supported value types.Pete Cooper2013-10-031-0/+1
| | | | | | This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion. llvm-svn: 191870
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-241-0/+3
| | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
* [Mips][msa] Value types for MSA support.Jack Carter2013-08-131-0/+1
| | | | | | | | | Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, and CodeGenTarget.cpp Patch by Daniel Sanders llvm-svn: 188326
* Add 'const' qualifier to some arrays.Craig Topper2013-07-151-1/+1
| | | | llvm-svn: 186312
* Extend 'readonly' and 'readnone' to work on function arguments as well asNick Lewycky2013-07-061-0/+6
| | | | | | | functions. Make the function attributes pass add it to known library functions and when it can deduce it. llvm-svn: 185735
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-171-1/+1
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64Elena Demikhovsky2012-12-241-0/+6
| | | | llvm-svn: 171026
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-3/+3
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-14/+15
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-191-0/+8
| | | | llvm-svn: 164261
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-111-6/+5
| | | | | | list of registers every time we want to look up a register by name. llvm-svn: 163659
* Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem2012-09-061-0/+2
| | | | | | | | allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). llvm-svn: 163299
* Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen2012-08-231-0/+9
| | | | | | | | | | | | Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. llvm-svn: 162460
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-1/+11
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* whitespaceAndrew Trick2012-07-071-3/+3
| | | | llvm-svn: 159890
* rdar://11542750 - llvm.trap should be marked no return.Chris Lattner2012-05-271-0/+3
| | | | llvm-svn: 157551
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-011-8/+0
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. llvm-svn: 151814
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-291-0/+8
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. llvm-svn: 151760
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-2/+2
| | | | llvm-svn: 149814
* Added MVT::v2f16Pete Cooper2012-01-121-0/+1
| | | | llvm-svn: 148067
* Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel2012-01-091-0/+20
| | | | | | | AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. llvm-svn: 147787
* Add basic generic CodeGen support for half.Dan Gohman2011-12-201-0/+1
| | | | llvm-svn: 146927
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-0/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-1/+1
| | | | llvm-svn: 144747
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-5/+5
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Unconstify InitsDavid Greene2011-07-291-2/+2
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Constify InitsDavid Greene2011-07-291-2/+2
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-2/+2
| | | | | | in multiple buildbots. llvm-svn: 134936
* [AVX] Make Inits FoldableDavid Greene2011-07-111-2/+2
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Add support for alternative register names, useful for instructions whose ↵Owen Anderson2011-06-271-0/+5
| | | | | | | | operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. llvm-svn: 133940
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-6/+4
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Fix formatting.Owen Anderson2011-06-161-1/+1
| | | | llvm-svn: 133164
* Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson2011-06-151-0/+1
| | | | | | features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. llvm-svn: 133106
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-5/+4
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen2011-06-151-11/+1
| | | | | | No functional change intended. llvm-svn: 133029
* Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen2011-06-111-14/+1
| | | | | | | Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. llvm-svn: 132865
* Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen2011-06-101-13/+8
| | | | | | | Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. llvm-svn: 132849
* Move TableGen's register bank classes to their own source file.Jakob Stoklund Olesen2011-06-091-73/+0
| | | | | | | | | | | I'll be moving some more code there to gather all of the register-specific stuff in one place. Currently it is shared between CodeGenTarget and RegisterInfoEmitter. The plan is that CodeGenRegisters can compute the full register bank structure while RegisterInfoEmitter only will handle the printing part. llvm-svn: 132788
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+1
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Change how tblgen generates attributes for intrinsics to use a singleJohn McCall2011-05-281-0/+6
| | | | | | | | | switch. With this newfound organization, teach tblgen how not to give all intrinsics the 'nounwind' attribute. Introduce a new intrinsic, llvm.eh.resume, which does not have this attribute. Documentation and uses to follow. llvm-svn: 132252
* Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen2011-05-071-3/+10
| | | | | | | The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. llvm-svn: 131058
* Don't allow per-register spill size and alignment.Jakob Stoklund Olesen2011-04-211-2/+0
| | | | | | | These values were not used for anything. Spill size and alignment is a property of the register class, not the register. llvm-svn: 129906
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-0/+1
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-111-0/+3
| | | | llvm-svn: 127448
* Trailing whitespace.Jim Grosbach2011-03-111-20/+20
| | | | llvm-svn: 127447
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-2/+2
| | | | llvm-svn: 122513
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* various cleanups to tblgen, patch by Garrison Venn!Chris Lattner2010-12-151-1/+1
| | | | llvm-svn: 121837
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