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path: root/llvm/utils/TableGen/CodeGenSchedule.cpp
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* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-061-12/+12
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-051-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [SchedModel] Complete models shouldn't match against itineraries when they ↵Simon Pilgrim2018-04-051-1/+2
| | | | | | | | | | | | don't use them (PR35639) For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp This patch causes problems for a number of models that had been incorrectly flagged as complete. Differential Revision: https://reviews.llvm.org/D43235 llvm-svn: 329280
* [MC][Tablegen] Allow the definition of processor register files in the ↵Andrea Di Biagio2018-04-031-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling model for llvm-mca This patch allows the description of register files in processor scheduling models. This addresses PR36662. A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td. Targets can optionally describe register files for their processors using that class. In particular, class RegisterFile allows to specify: - The total number of physical registers. - Which target registers are accessible through the register file. - The cost of allocating a register at register renaming stage. Example (from this patch - see file X86/X86ScheduleBtVer2.td) def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]> Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register. The syntax allows to specify an empty set of register classes. An empty set of register classes means: this register file models all the registers specified by the Target. For each register class, users can specify an optional register cost. By default, register costs default to 1. A value of 0 for the number of physical registers means: "this register file has an unbounded number of physical registers". This patch is structured in two parts. * Part 1 - MC/Tablegen * A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files. Information about register files is accessible through an instance of MCExtraProcessorInfo. The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers. I think that this design would make easier for targets to get rid of the extra processor information if they don't want it. * Part 2 - llvm-mca related * The second part of this patch is related to changes to llvm-mca. The main differences are: 1) class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage. 2) Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction. 3) The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor. The effect of point 3. is also visible in tests register-files-[1..5].s. Differential Revision: https://reviews.llvm.org/D44980 llvm-svn: 329067
* [SchedModel] Remove instregex entries that don't match any instructionsSimon Pilgrim2018-03-251-2/+11
| | | | | | | | | | This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean. All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced. Differential Revision: https://reviews.llvm.org/D44687 llvm-svn: 328459
* [SchedModel] Remove an unneeded temporary vector.Craig Topper2018-03-241-3/+2
| | | | llvm-svn: 328442
* [SchedModel] Use std::move in a couple places to reduce copyingCraig Topper2018-03-241-2/+3
| | | | llvm-svn: 328441
* [SchedModel] Use std::move to replace a vector instead of vector::swapCraig Topper2018-03-241-1/+1
| | | | | | We don't really care about the old vector value so we don't care to swap it. llvm-svn: 328440
* [SchedModel] Remove std::vectors that were created with 1 element and then ↵Craig Topper2018-03-241-8/+5
| | | | | | | | passed to an ArrayRef parameter. ArrayRef can capture a single element. We don't need a vector for that. llvm-svn: 328438
* [SchedModel] Record::getName() returns StringRef - avoid std::string ↵Simon Pilgrim2018-03-241-2/+2
| | | | | | creation. NFCI. llvm-svn: 328437
* [SchedModel] Avoid std::string creation for instregex patterns that don't ↵Simon Pilgrim2018-03-241-2/+3
| | | | | | contain regex metas. NFCI. llvm-svn: 328436
* [TableGen] Use empty emplace_back to add defaulted constructed objects to ↵Craig Topper2018-03-221-10/+8
| | | | | | vectors to avoid using resize(size()+1). NFC llvm-svn: 328184
* [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via ↵Craig Topper2018-03-221-14/+9
| | | | | | emplace_back to create new SchedClasses instead of using resize(size+1) llvm-svn: 328183
* [TableGen] Hoist the code for copying InstRWs from an old scheduling class ↵Craig Topper2018-03-211-12/+12
| | | | | | | | | | to a new one out of the loop that assigns instructions to the new class. NFCI We already know all the of instructions we're processing in the instruction loop belong to no class or all to the same class. So we only have to worry about remapping one class. So hoist it all out and remove the SmallPtrSet that tracked which class we'd already remapped. I had to introduce new instruction loop inside this code to print an error message, but that only occurs on the error path. llvm-svn: 328142
* [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCICraig Topper2018-03-211-1/+0
| | | | | | We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs. llvm-svn: 328139
* [TableGen] Use range-based for loops. NFCCraig Topper2018-03-211-12/+11
| | | | llvm-svn: 328138
* [TableGen] Use count_if instead of a manual loop. NFCCraig Topper2018-03-211-5/+4
| | | | llvm-svn: 328137
* [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.Simon Pilgrim2018-03-211-1/+1
| | | | llvm-svn: 328128
* [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. ↵Simon Pilgrim2018-03-211-5/+2
| | | | | | NFCI. llvm-svn: 328126
* [TableGen] Remove a defaulted function argument that is never called with ↵Craig Topper2018-03-211-4/+2
| | | | | | another value. NFC llvm-svn: 328075
* [TableGen] Move a function from llvm namespace and make it a static ↵Craig Topper2018-03-211-6/+2
| | | | | | | | function. NFC It's only called from one place and is defined just above that use. llvm-svn: 328074
* [TableGen] Use SmallMapVector to simplify some code that was trying to keep ↵Craig Topper2018-03-211-14/+6
| | | | | | | | | | | | | | | | | | | | | a vector unique Summary: This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order. We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much. We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation. Reviewers: RKSimon, dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44711 llvm-svn: 328070
* [SchedModel] Simplify InstRegexOp::apply. NFCI.Simon Pilgrim2018-03-201-24/+27
| | | | | | As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions. llvm-svn: 328052
* [TableGen] Use range based for loop. NFCCraig Topper2018-03-201-5/+2
| | | | llvm-svn: 328034
* [TableGen] Use vector::append instead of looping and calling push_back. NFCCraig Topper2018-03-201-4/+2
| | | | | | Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed. llvm-svn: 328033
* [TableGen] Use llvm::transform to simplify some loops. NFCICraig Topper2018-03-201-18/+12
| | | | llvm-svn: 328032
* [TableGen] Pass result of std::unique to vector::erase instead of ↵Craig Topper2018-03-201-2/+1
| | | | | | calculating a size and calling resize. llvm-svn: 328031
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-181-1/+14
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* [TableGen] Remove unnecessary uses of make_range.Craig Topper2018-03-181-2/+2
| | | | llvm-svn: 327785
* [TableGen] Move some variables into for loop declaration. NFCCraig Topper2018-03-181-2/+1
| | | | | | They aren't needed after the loop. llvm-svn: 327784
* [CodeGenSchedule][NFC] Always emit ProcResourceUnits.Clement Courbet2018-02-051-0/+8
| | | | | | | | | | | | | | | | | Summary: Right now only the ProcResourceUnits that are directly referenced by instructions are emitted. This change emits all of them, so that analysis passes can use the information. This has no functional impact. It typically adds a few entries (e.g. 4 for X86/haswell) to the generated ProcRes table. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42903 llvm-svn: 324228
* [TableGen] Add a way of getting the number of generic opcodes without ↵Benjamin Kramer2018-01-241-5/+4
| | | | | | | | | | including modular CodeGen headers. This is a bit of a hack, but removes a cycle that broke modular builds of LLVM. Of course the cycle is still there in form of a dependency on the .def file. llvm-svn: 323383
* [TableGen] Optimize the regex search.Benjamin Kramer2018-01-231-20/+76
| | | | | | | | | | | | | | | | llvm::Regex is still the slowest regex engine on earth, running it over all instructions on X86 takes a while. Extract a prefix and use a binary search to reduce the search space before we resort to regex matching. There are a couple of caveats here: - The generic opcodes are outside of the sorted enum. They're handled in an extra loop. - If there's a top-level bar we can't use the prefix trick. - We bail on top-level ?. This could be handled, but it's rare. This brings the time to generate X86GenInstrInfo.inc from 21s to 4.7s on my machine. llvm-svn: 323277
* [TableGen] Improve error reportingEvandro Menezes2017-11-211-7/+9
| | | | | | | | | When searching for a resource unit, use the reference location instead of the definition location in case of an error. Differential revision: https://reviews.llvm.org/D40263 llvm-svn: 318803
* [TableGen] Tidy up CodeGenSchedule.cppJaved Absar2017-10-111-13/+13
| | | | | | Use range_loop where it simplifies. llvm-svn: 315446
* [TableGen] Convert VarDef to range_loop. NFC.Javed Absar2017-10-101-2/+2
| | | | llvm-svn: 315321
* [TableGen] remove make_range where not necessaryJaved Absar2017-10-091-6/+5
| | | | llvm-svn: 315209
* [TableGen] Simplify, add range_loop in CodeGenScheduleJaved Absar2017-10-081-11/+10
| | | | llvm-svn: 315183
* [TablgeGen] : Tidy up CodeGenSchedule. NFC.Javed Absar2017-10-051-25/+21
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38534 llvm-svn: 314982
* [MiSched|TableGen] : Tidy up and modernise. NFC.Javed Absar2017-09-131-103/+89
| | | | | | | | | Replacing with range-based loop and substituting 'using'. Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D37748 llvm-svn: 313140
* [TableGen] Improve Debug Output for --debug-only=subtarget-emitter NFCIJoel Jones2017-06-281-0/+7
| | | | | | | | | Add headers for each section of output, with white space and "+++" to improve readability. Differential Revision: https://reviews.llvm.org/D34713 llvm-svn: 306492
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-1/+1
| | | | | | instead of a std::string. llvm-svn: 304347
* Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2016-11-301-16/+27
| | | | | | This preparation to remove SetVector.h dependency on SmallSet.h. llvm-svn: 288256
* Fix per-processor model scheduler definition completeness checkUlrich Weigand2016-10-311-1/+2
| | | | | | | | | | | | | | | The CodeGenSchedModels::checkCompleteness routine in TableGen/ CodeGenSchedule.cpp is supposed to verify for each processor model that is marked as "complete" that it actually defines a scheduling class for each instruction. However, this did not work correctly due to an incorrect check whether a scheduling class has an itinerary. Reviewer: atrick Differential revision: https://reviews.llvm.org/D26156 llvm-svn: 285622
* Improve tablegen gen-subtarget diagnostics for missing machine models.Andrew Trick2016-10-181-5/+8
| | | | | | | | | | | | -debug-only=subtarget-emitter prints a lot of machine model diagnostics. This prunes the output so that the "No machine model for XXX on processor YYY" only appears when there is definitely no machine model for that opcode. Previously it was printing that error even if the opcode was covered by a more general scheduling class. <rdar://problem/15919845> [TableGen][CodeGenSchedule] Debug output does not help spotting the missing scheduling classes llvm-svn: 284452
* Use the range variant of find/find_if instead of unpacking begin/endDavid Majnemer2016-08-121-10/+4
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278469
* Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2016-08-121-5/+3
| | | | | | No functionality change is intended. llvm-svn: 278443
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-8/+5
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* Revert "Revert "[misched] Extend scheduler to handle unsupported features""Simon Dardis2016-06-241-1/+29
| | | | | | | | This reverts commit r273565. This was an over-eager revert. llvm-svn: 273658
* Revert "[misched] Extend scheduler to handle unsupported features"Simon Dardis2016-06-231-29/+1
| | | | | | | | This reverts commit r273551. Patch contained a wrong check for isUnsupported. llvm-svn: 273565
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