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path: root/llvm/utils/TableGen/CodeGenSchedule.cpp
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* Fix a tblgen subtargetemitter bug, for future Swift support.Andrew Trick2013-06-051-4/+23
| | | | | | | | | | This fixes some of the ridiculously complex code for optimizing the machine model tables that are shared among all processors of a given target. A9 and Swift both use the "special" feature that maps old itinerary classes to new machine model defs. They map different overlapping subsets of instructions, which wasn't handled correctly. llvm-svn: 183302
* Machine model: verify well-formed processor resource groups.Andrew Trick2013-04-231-0/+51
| | | | llvm-svn: 180161
* Fix TableGen subtarget-emitter to handle A9/Swift.Andrew Trick2013-03-291-5/+11
| | | | | | | | A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. llvm-svn: 178357
* Revert r178166. According to Howard, this code is actually ok.Dan Gohman2013-03-291-3/+1
| | | | llvm-svn: 178319
* Avoid undefined behavior from passing a std::vector's own contentsDan Gohman2013-03-271-1/+3
| | | | | | in as an argument to push_back. llvm-svn: 178166
* TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick2013-03-261-1/+8
| | | | | | Allow variants to be defined only for some processors on a target. llvm-svn: 178074
* TableGen fix for the new machine model.Andrew Trick2013-03-181-4/+6
| | | | | | | | Properly handle cases where a group of instructions have different SchedRW lists with the same itinerary class. This was supposed to work, but I left in an early break. llvm-svn: 177317
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-161-123/+111
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
* Add SchedRW as an Instruction field.Jakob Stoklund Olesen2013-03-151-6/+6
| | | | | | | | | | | | | Don't require instructions to inherit Sched<...>. Sometimes it is more convenient to say: let SchedRW = ... in { ... } Which is now possible. llvm-svn: 177199
* MachineModel: Add a ProcResGroup class.Andrew Trick2013-03-141-0/+17
| | | | | | | | | | | | | | | | | This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; llvm-svn: 177112
* MachineModel: Inconsequential TableGen SubtargetEmitter fix.Andrew Trick2013-02-011-1/+15
| | | | | | | | Drive by fix. I noticed some missing logic that might bite future users. This shouldn't affect the final output on currently modeled targets. llvm-svn: 174142
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Fix a build problem with xlc. The error message wasRafael Espindola2012-11-021-1/+1
| | | | | | | | | "../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+". "../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate. Patch by Kai. llvm-svn: 167311
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-28/+30
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Don't use stack unwinding to provide the location information forJoerg Sonnenberger2012-10-241-4/+7
| | | | | | SetTheory, but pass down the location explicitly. llvm-svn: 166629
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-1/+1
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* TableGen subtarget emitter cleanup.Andrew Trick2012-10-101-29/+36
| | | | | | Consistently evaluate Aliases and Sequences recursively. llvm-svn: 165604
* Added instregex support to TableGen subtarget emitter.Andrew Trick2012-10-031-9/+75
| | | | | | | | This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. llvm-svn: 165180
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-031-112/+199
| | | | | | | | | A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. llvm-svn: 165179
* Cleanup TableGen subtarget emitter.Andrew Trick2012-10-031-4/+1
| | | | llvm-svn: 165178
* Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick2012-09-221-57/+190
| | | | | | | Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. llvm-svn: 164451
* SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick2012-09-191-0/+15
| | | | llvm-svn: 164199
* TableGen subtarget parser: Add getProcResourcesIdx().Andrew Trick2012-09-171-0/+10
| | | | llvm-svn: 164057
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-0/+190
| | | | | | Collect processor resources from the subtarget defs. llvm-svn: 163953
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-0/+495
| | | | | | Infer SchedClasses from variants defined by the target or subtarget. llvm-svn: 163952
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-78/+585
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. llvm-svn: 163951
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-0/+151
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
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