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* Order register classes topologically.Jakob Stoklund Olesen2011-09-301-0/+1
| | | | | | | | | All register classes are given a lower ID than their sub-classes. Cliques are ordered alphabetically. This will be used to simplify some sub-class operations. llvm-svn: 140826
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-2/+2
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-2/+2
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Remove MethodProtos/MethodBodies and allocation_order_begin/end.Jakob Stoklund Olesen2011-06-181-1/+1
| | | | | | | | | | | | | | Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. llvm-svn: 133332
* Provide AltOrders for specifying alternative allocation orders.Jakob Stoklund Olesen2011-06-181-3/+11
| | | | | | | | | | | | A register class can define AltOrders and AltOrderSelect instead of defining method protos and bodies. The AltOrders lists can be defined with set operations, and TableGen can verify that the alternative allocation orders only contain valid registers. This is currently an opt-in feature, and it is still possible to override allocation_order_begin/end. That will not be true for long. llvm-svn: 133320
* Use a SetTheory instance to expand register lists in register classes.Jakob Stoklund Olesen2011-06-151-2/+7
| | | | | | | | This prepares tablegen to compute register lists from set theoretic dag expressions. This doesn't really make any difference as long as Target.td still declares RegisterClass::MemberList as [Register]. llvm-svn: 133043
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-30/+17
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen2011-06-151-0/+17
| | | | | | No functional change intended. llvm-svn: 133029
* Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen2011-06-121-0/+34
| | | | | | | | | | | | | | | | | | | | | | | Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. llvm-svn: 132881
* Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen2011-06-111-14/+48
| | | | | | | Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. llvm-svn: 132865
* Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen2011-06-101-0/+27
| | | | | | | Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. llvm-svn: 132849
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+1
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Don't allow per-register spill size and alignment.Jakob Stoklund Olesen2011-04-211-1/+0
| | | | | | | These values were not used for anything. Spill size and alignment is a property of the register class, not the register. llvm-svn: 129906
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-0/+1
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-111-0/+1
| | | | llvm-svn: 127448
* Trailing whitespace.Jim Grosbach2011-03-111-4/+4
| | | | llvm-svn: 127446
* add (and document) the ability for alias results to haveChris Lattner2010-11-061-0/+6
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* Split out register class subclassing to a separate function and clean upEric Christopher2010-08-251-0/+32
| | | | | | accordingly. No functional change. llvm-svn: 112008
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-1/+3
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-3/+3
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-3/+3
| | | | | | own struct type. llvm-svn: 78610
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-3/+3
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Unbreak build with gcc 4.3: provide missed includes and silence most ↵Anton Korobeynikov2008-02-201-1/+2
| | | | | | annoying warnings. llvm-svn: 47367
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+1
| | | | | | between two registers in the specific class. llvm-svn: 42123
* Remove spurious consts. This fixes warnings with compilers thatDan Gohman2007-09-141-1/+1
| | | | | | are strict about such things. llvm-svn: 41956
* Add support to tablegen for specifying subregister classes on a per register ↵Christopher Lamb2007-06-131-0/+1
| | | | | | class basis. llvm-svn: 37572
* Add support for generating v4i32 altivec codeNate Begeman2005-12-301-1/+1
| | | | llvm-svn: 25046
* Add some methodsChris Lattner2005-12-051-0/+2
| | | | llvm-svn: 24596
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-1/+8
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Compute the value types that are natively supported by a target.Chris Lattner2005-09-081-0/+2
| | | | llvm-svn: 23282
* Split register class "Methods" into MethodProtos and MethodBodiesChris Lattner2005-08-191-1/+1
| | | | llvm-svn: 22928
* Read the namespace field from register classesChris Lattner2005-08-191-0/+1
| | | | llvm-svn: 22918
* Remove trailing whitespaceMisha Brukman2005-04-221-2/+2
| | | | llvm-svn: 21428
* Support "Methods" in register classes in CodgeGenRegisterClassChris Lattner2004-08-211-1/+1
| | | | llvm-svn: 15965
* Start parsing register classes into a more structured formChris Lattner2004-08-211-0/+8
| | | | llvm-svn: 15961
* Read in declared reg sizesChris Lattner2004-08-211-1/+2
| | | | llvm-svn: 15960
* Add initial support for register and register class representation.Chris Lattner2004-08-161-0/+37
Obviously this is not done. llvm-svn: 15804
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