summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/CodeGenRegisters.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Assume lane masks are always preciseMatthias Braun2015-11-171-13/+6
| | | | | | | | | | | | | | | Allowing imprecise lane masks in case of more than 32 sub register lanes lead to some tricky corner cases, and I need another bugfix for another one. Instead I rather declare lane masks as precise and let tablegen abort if we do not have enough bits. This does not affect any in-tree target, even AMDGPU only needs 16 lanes at the moment. If the 32 lanes turn out to be a problem in the future, then we can easily change the LaneBitmask typedef to uint64_t. Differential Revision: http://reviews.llvm.org/D14557 llvm-svn: 253279
* tablegen: Add a simple heuristic to get better names for pressure setsMatthias Braun2015-11-131-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D14597 llvm-svn: 253095
* TableGen: Emit LaneMask for register classes without subregisters as ~0uMatthias Braun2015-11-101-0/+6
| | | | | | | This makes it slightly easier to handle classes with and without subregister uniformly. llvm-svn: 252671
* [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper2015-06-021-3/+3
| | | | llvm-svn: 238806
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-291-2/+2
| | | | | | | | | | | | | | | | | | | | If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
* [TableGen] Remove ListInit::size() in favor of getSize() which does the same ↵Craig Topper2015-05-141-2/+2
| | | | | | thing and is already used in most places. NFC. llvm-svn: 237341
* [TableGen] Don't leak Expanders and Operators in SetTheory.Craig Topper2015-04-241-1/+1
| | | | llvm-svn: 235697
* Change range-based for-loops to be -Wrange-loop-analysis clean.Richard Trieu2015-04-151-1/+1
| | | | | | No functionality change. llvm-svn: 234963
* Fix AllocationPriority not getting set for derived register classes.Matthias Braun2015-03-311-1/+3
| | | | llvm-svn: 233752
* RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun2015-03-311-0/+4
| | | | | | | | | | Specify an allocation order with a register class. This is used by register allocators with a greedy heuristic. This is usefull as it is sometimes beneficial to color more constrained classes first. Differential Revision: http://reviews.llvm.org/D8626 llvm-svn: 233743
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-191-0/+11
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* TableGen: Fix register class lane masks being too conservative.Matthias Braun2015-03-181-1/+1
| | | | | | | | | | | | | | When calculating the lanemask of a register class we have to include the masks of subregisters supported by any of the class members, not just the ones supported by all class members. This fixes problems when coalescing towards a subclass with additional subregisters available. The attached testcase works fine as is, but does crash if you enable subregister liveness on x86 without this change applied. llvm-svn: 232652
* Revert the non-cleanup part of r230769 because it introduced a ↵Nick Lewycky2015-03-031-2/+0
| | | | | | non-determinism found only in the names of symbols. llvm-svn: 231058
* Silence variable set but not used warning in CodeGenRegisters.cpp, NFC.Yaron Keren2015-02-281-0/+1
| | | | llvm-svn: 230854
* Switch a std::map to a DenseMap in CodeGenRegisters.Owen Anderson2015-02-271-0/+2
| | | | | | | | The keys of the map are unique by pointer address, so there's no need to use the llvm::less comparator. This allows us to use DenseMap instead, which reduces tblgen time by 20% on my stress test. llvm-svn: 230769
* MSVC 2013 does not ICE on this code in the same fashion that MSVC 2012 did; NFC.Aaron Ballman2015-02-161-3/+1
| | | | llvm-svn: 229422
* STLExtras: Provide less/equal functors with templated function call ↵David Blaikie2015-02-021-12/+11
| | | | | | | | | | | | | | | | operators, plus a deref'ing functor template utility Similar to the C++14 void specializations of these templates, useful as a stop-gap until LLVM switches to '14. Example use-cases in tblgen because I saw some functors that looked like they could be simplified/refactored. Reviewers: dexonsmith Differential Revision: http://reviews.llvm.org/D7324 llvm-svn: 227828
* Replace another std::set in the core of CodeGenRegister, this time with ↵Owen Anderson2015-01-311-39/+46
| | | | | | | | sorted arrays. The hot path through this region of code does lots of batch inserts into sets. By storing them as sorted arrays, we can defer the sorting to the end of the batch, which is dramatically more efficient. This reduces tblgen runtime by 25% on my worst-case target. llvm-svn: 227682
* Change more of the guts of CodeGenRegister's RegUnit tracking to be based on ↵Owen Anderson2015-01-311-54/+29
| | | | | | | | bit vectors. This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case. llvm-svn: 227678
* Change a very hot piece of code in TableGen's register unit computations to ↵Owen Anderson2015-01-301-1/+14
| | | | | | | | | | | | | | | | use bit vectors rather than arrays. For target descriptions with very large and very dense register files, TableGen can take an extremely long time to run. This change makes a dent in that (~15% in my measurements) by accelerating the single hottest operation with better data structures. I believe there's still a lot of room to make this even faster with more global changes that require replacing some of the existing datastructures in this area with bit vectors, but that's a more involved change and I wanted to get this simpler improvement in first. llvm-svn: 227562
* Clean up static analyzer warnings.Michael Ilseman2014-12-121-0/+1
| | | | | | | | | Clang's static analyzer found several potential cases of undefined behavior, use of un-initialized values, and potentially null pointer dereferences in tablegen, Support, MC, and ADT. This cleans them up with specific assertions on the assumptions of the code. llvm-svn: 224154
* Tablegen'erate lanemasks for register units.Matthias Braun2014-12-101-0/+37
| | | | | | Now we can relate lanemasks in a virtual register to register units. llvm-svn: 223889
* Add function that translates subregister lane masks to other subregs.Matthias Braun2014-12-101-0/+64
| | | | | | | This works like the composeSubRegisterIndices() function but transforms a subregister lane mask instead of a subregister index. llvm-svn: 223874
* Let tablegen compute maximum lanemask for regs/regclasses.Matthias Braun2014-12-101-3/+15
| | | | | | | | Let tablegen compute the combination of subregister lanemasks for all subregisters in a register/register class. This is preparation for further work subregister allocation llvm-svn: 223873
* range-for some thingsDavid Blaikie2014-12-031-19/+12
| | | | llvm-svn: 223263
* Simplify CodeGenRegBank::inferMatchingSuperRegClass & its caller by passing ↵David Blaikie2014-12-031-16/+16
| | | | | | an iterator rather than index llvm-svn: 223262
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-57/+59
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-58/+66
| | | | | | range-for isn't suitable. llvm-svn: 223260
* Remove some unnecessary vector::reserve/assign calls.David Blaikie2014-11-291-9/+5
| | | | llvm-svn: 222959
* Remove indirection of vector<T*> in favor of deque<T>David Blaikie2014-11-291-36/+32
| | | | llvm-svn: 222958
* Use deque<T> rather than vector<T*> since it provides the same invalidation ↵David Blaikie2014-11-291-27/+19
| | | | | | | | | | | | | | | semantics (at least when removal is not needed) without the extra indirection/ownership complexity Order matters for this container, it seems (using a forward_list and replacing the original push_backs with emplace_fronts caused test failures). I didn't look too deeply into why. (& in retrospect, I might go back & change some of the forward_lists I introduced to deques anyway - since most don't require removal, deque is a more memory-friendly data structure (moderate locality while not invalidating pointers)) llvm-svn: 222950
* Constify some things in preparation for CodeGenSubRegIndex to be stored by ↵David Blaikie2014-11-291-22/+21
| | | | | | value in their container, removing the indirection llvm-svn: 222949
* Fix a few memory leaks in CodeGenRegBank.Craig Topper2014-11-281-0/+6
| | | | llvm-svn: 222930
* Remove StringMap::GetOrCreateValue in favor of StringMap::insertDavid Blaikie2014-11-191-3/+6
| | | | | | | | | | | | | | Having two ways to do this doesn't seem terribly helpful and consistently using the insert version (which we already has) seems like it'll make the code easier to understand to anyone working with standard data structures. (I also updated many references to the Entry's key and value to use first() and second instead of getKey{Data,Length,} and get/setValue - for similar consistency) Also removes the GetOrCreateValue functions so there's less surface area to StringMap to fix/improve/change/accommodate move semantics, etc. llvm-svn: 222319
* Fix some cases were ArrayRefs were being passed by reference. Also remove ↵Craig Topper2014-08-271-1/+1
| | | | | | 'const' from some other ArrayRef uses since its implicitly const already. llvm-svn: 216524
* Use range based for loops to avoid needing to re-mention SmallPtrSet size.Craig Topper2014-08-241-3/+2
| | | | llvm-svn: 216351
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-6/+6
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-291-1/+1
| | | | | | No functionality change. llvm-svn: 205110
* [C++11] Add 'override' keywords to tablegen code.Craig Topper2014-03-051-1/+1
| | | | llvm-svn: 202937
* [C++11] Use std::tie to simplify compare operators.Benjamin Kramer2014-03-031-5/+2
| | | | | | No functionality change. llvm-svn: 202751
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
| | | | | | Remove the old functions. llvm-svn: 202636
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-11/+4
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to ↵Craig Topper2014-01-241-1/+1
| | | | | | facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). llvm-svn: 200036
* Provide basic type safety for array_pod_sort comparators.Benjamin Kramer2013-09-221-3/+4
| | | | | | | | This makes using array_pod_sort significantly safer. The implementation relies on function pointer casting but that should be safe as we're dealing with void* here. llvm-svn: 191175
* comment typo.Andrew Trick2013-07-311-1/+1
| | | | llvm-svn: 187531
* Fix register pressure tables on ARM.Andrew Trick2013-07-311-3/+31
| | | | | | The heuristic that merges register pressure sets was bogus for ARM's S/D regs. llvm-svn: 187479
* Add tracing to the tblgen register pressure table generator.Andrew Trick2013-07-311-7/+63
| | | | llvm-svn: 187478
* RegPressure: Order the "pressure sets" by number of regunits per set.Andrew Trick2013-07-251-1/+26
| | | | | | This lets heuristics easily pick the most important set to follow. llvm-svn: 187108
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-1/+1
| | | | | | size. llvm-svn: 186274
OpenPOWER on IntegriCloud