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path: root/llvm/utils/TableGen/CodeGenRegisters.cpp
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* Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen2012-05-091-0/+16
| | | | | | | | | | | | | | | | This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. llvm-svn: 156519
* Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen2012-05-091-8/+9
| | | | | | That's what it does. llvm-svn: 156518
* Order register classes by spill size first, members last.Jakob Stoklund Olesen2012-05-041-7/+7
| | | | | | | | | | | | This is still a topological ordering such that every register class gets a smaller enum value than its sub-classes. Placing the smaller spill sizes first makes a difference for the super-register class bit masks. When looking for a super-register class, we usually want the smallest possible kind of super-register. That is now available as the first bit set in the bit mask. llvm-svn: 156222
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-041-23/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* tblgen: remove duplicated newlines.Benjamin Kramer2012-04-181-1/+1
| | | | llvm-svn: 155038
* Move a few more warnings to use PrintWarning().Jim Grosbach2012-04-181-5/+5
| | | | llvm-svn: 155027
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-111-13/+12
| | | | llvm-svn: 154518
* TableGen'd regpressure: register unit set pruning.Andrew Trick2012-04-111-18/+14
| | | | | | | The pruning is more complete if it is not done incrementally. The code is also a tad less convluted. llvm-svn: 154510
* Table-generated register pressure fixes.Andrew Trick2012-04-111-24/+47
| | | | | | | Handle mixing allocatable and unallocatable register gracefully. Simplify the pruning of register unit sets. llvm-svn: 154474
* TableGen/reginfo potential bug: typo from previous checkin.Andrew Trick2012-04-101-1/+1
| | | | llvm-svn: 154452
* Fix for register pressure tables.Andrew Trick2012-04-101-13/+15
| | | | | | Recent refactoring introduced a bug. Fix: added buildRegUnitSets. llvm-svn: 154382
* Use std::includes instead of my own implementation.Andrew Trick2012-04-101-9/+2
| | | | | | Jakob's review. llvm-svn: 154377
* Added register unit sets to the target description.Andrew Trick2012-04-101-0/+167
| | | | | | | | | | This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. llvm-svn: 154374
* Added register unit weights to the target description.Andrew Trick2012-04-101-17/+306
| | | | | | | | | | | | This is a new algorithm that associates registers with weighted register units to accuretely model their effect on register pressure. This handles registers with multiple overlapping subregisters. It is possible, but almost inconceivable that the algorithm fails to find an exact solution for a target description. If an exact solution cannot be found, an inexact, but reasonable solution will be chosen. llvm-svn: 154373
* Cleanup set_union usage. The same thing but a bit cleaner now.Andrew Trick2012-04-031-1/+1
| | | | llvm-svn: 153922
* Use std::set_union instead of nasty custom code.Andrew Trick2012-04-031-13/+3
| | | | | | | I just noticed Jakob's examples of the proper application of std::set... routines. llvm-svn: 153918
* comment typoAndrew Trick2012-03-311-1/+1
| | | | llvm-svn: 153796
* Introduce Register Units: Give each leaf register a number.Andrew Trick2012-03-311-0/+49
| | | | | | | | First small step toward modeling multi-register multi-pressure. In the future, register units can also be used to model liveness and aliasing. llvm-svn: 153794
* Add more constness to CodeGenRegisters.Jakob Stoklund Olesen2012-03-291-3/+3
| | | | llvm-svn: 153667
* Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen2012-02-011-25/+74
| | | | | | | | | | | | | | | | | It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. llvm-svn: 149556
* Fix a bug in the TopoOrderRC comparison function.Jakob Stoklund Olesen2012-02-011-1/+1
| | | | | | | | | | | The final tie breaker comparison also needs to return +/-1, or 0. This is not a less() function. This could cause otherwise identical super-classes to be ordered unstably, depending on what the system qsort routine does with a bad compare function. llvm-svn: 149549
* Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen2012-01-311-20/+21
| | | | | | Each SubRegIndex keeps track of how it composes. llvm-svn: 149423
* Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen2012-01-311-37/+80
| | | | | | | | | This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. llvm-svn: 149418
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-12/+40
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
* Add TableGen support for callee saved registers.Jakob Stoklund Olesen2012-01-171-0/+23
| | | | | | | | | Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). llvm-svn: 148346
* Skip the NAME field when forming tuples.Jakob Stoklund Olesen2012-01-131-0/+3
| | | | llvm-svn: 148147
* Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen2012-01-131-1/+1
| | | | | | | The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. llvm-svn: 148092
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-191-1/+15
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Synthesize register classes for TRI::getMatchingSuperRegClass().Jakob Stoklund Olesen2011-12-191-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Teach TableGen to create the missing register classes needed for getMatchingSuperRegClass() to return maximal results. The function is still not auto-generated, so it still returns inexact results. This produces these new register classes: ARM: QQPR_with_dsub_0_in_DPR_8 QQQQPR_with_dsub_0_in_DPR_8 X86: GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP GR64_with_sub_16bit_in_GR16_NOREX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_with_sub_32bit_in_GR32_TC GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC GR64_with_sub_32bit_in_GR32_AD GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX The other targets in the tree are not weird enough to be affected. llvm-svn: 146872
* Extract a method. No functional change.Jakob Stoklund Olesen2011-12-161-36/+46
| | | | llvm-svn: 146713
* Use the proper comparator for set_intersection.Jakob Stoklund Olesen2011-12-151-1/+2
| | | | llvm-svn: 146674
* Synthesize missing register class intersections.Jakob Stoklund Olesen2011-12-151-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function TRI::getCommonSubClass(A, B) returns the largest common sub-class of the register classes A and B. This patch teaches TableGen to synthesize sub-classes such that the answer is always maximal. In other words, every register that is in both A and B will also be present in getCommonSubClass(A, B). This introduces these synthetic register classes: ARM: GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR tGPR_and_tcGPR hGPR_and_tcGPR X86: GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR64_NOSP_and_GR64_TC GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_TC GR32_NOAX_and_GR32_NOSP GR64_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_ABCD_and_GR32_NOAX GR64_ABCD_and_GR64_TC GR32_NOAX_and_GR32_TC GR32_AD_and_GR32_NOAX Other targets are unaffected. llvm-svn: 146657
* Extract a method.Jakob Stoklund Olesen2011-12-121-14/+21
| | | | llvm-svn: 146374
* Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen2011-10-051-6/+14
| | | | | | | | | | | | | | | | This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. llvm-svn: 141142
* Properly use const_iterator.Jakob Stoklund Olesen2011-10-041-4/+4
| | | | | | This should unbreak the Windows build. llvm-svn: 141105
* Teach TableGen to infer missing register classes.Jakob Stoklund Olesen2011-10-041-16/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. llvm-svn: 141084
* TableGen: Store all allocation orders together.Jakob Stoklund Olesen2011-10-041-7/+11
| | | | | | There is no need to keep the primary order separate. llvm-svn: 141082
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-041-3/+6
| | | | | | | | When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. llvm-svn: 141081
* TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen2011-10-041-1/+0
| | | | | | | The RecordKeeper could be shared by multiple target instances, causing duplicate record errors. llvm-svn: 141080
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().Jakob Stoklund Olesen2011-09-301-7/+8
| | | | | | | All the sub-class bit vectors are computed when first creating the register bank. llvm-svn: 140905
* Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen2011-09-301-0/+10
| | | | | | | Use these lists instead of computing them on the fly in RegisterInfoEmitter. llvm-svn: 140895
* Precompute a bit vector of register sub-classes.Jakob Stoklund Olesen2011-09-301-0/+29
| | | | llvm-svn: 140827
* Order register classes topologically.Jakob Stoklund Olesen2011-09-301-1/+40
| | | | | | | | | All register classes are given a lower ID than their sub-classes. Cliques are ordered alphabetically. This will be used to simplify some sub-class operations. llvm-svn: 140826
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-8/+7
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Unconstify InitsDavid Greene2011-07-291-12/+12
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Create Inits Via Factory MethodDavid Greene2011-07-291-3/+3
| | | | | | | Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. llvm-svn: 136486
* [AVX] Constify InitsDavid Greene2011-07-291-12/+12
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* Intern all RecTy subclass instances to avoid duplicates.Jakob Stoklund Olesen2011-07-181-2/+2
| | | | | | | | | | | | | | | | | Make all of the RecTy constructors private, and use get() factory methods instead. Return singleton instances when it makes sense. ListTy instance pointers are stored in the element RecTy instance. BitsRecTy instance pointers, one per length, are stored in a static vector. Also unique DefInit instances. A Record has a unique DefInit which has a unique RecordRecTy instance. This saves some 200k-300k RecTy allocations when parsing ARM.td. It reduces TableGen's heap usage by almost 50%. llvm-svn: 135399
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-16/+15
| | | | | | in multiple buildbots. llvm-svn: 134936
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