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path: root/llvm/utils/TableGen/CodeGenRegisters.cpp
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* Silence variable set but not used warning in CodeGenRegisters.cpp, NFC.Yaron Keren2015-02-281-0/+1
| | | | llvm-svn: 230854
* Switch a std::map to a DenseMap in CodeGenRegisters.Owen Anderson2015-02-271-0/+2
| | | | | | | | The keys of the map are unique by pointer address, so there's no need to use the llvm::less comparator. This allows us to use DenseMap instead, which reduces tblgen time by 20% on my stress test. llvm-svn: 230769
* MSVC 2013 does not ICE on this code in the same fashion that MSVC 2012 did; NFC.Aaron Ballman2015-02-161-3/+1
| | | | llvm-svn: 229422
* STLExtras: Provide less/equal functors with templated function call ↵David Blaikie2015-02-021-12/+11
| | | | | | | | | | | | | | | | operators, plus a deref'ing functor template utility Similar to the C++14 void specializations of these templates, useful as a stop-gap until LLVM switches to '14. Example use-cases in tblgen because I saw some functors that looked like they could be simplified/refactored. Reviewers: dexonsmith Differential Revision: http://reviews.llvm.org/D7324 llvm-svn: 227828
* Replace another std::set in the core of CodeGenRegister, this time with ↵Owen Anderson2015-01-311-39/+46
| | | | | | | | sorted arrays. The hot path through this region of code does lots of batch inserts into sets. By storing them as sorted arrays, we can defer the sorting to the end of the batch, which is dramatically more efficient. This reduces tblgen runtime by 25% on my worst-case target. llvm-svn: 227682
* Change more of the guts of CodeGenRegister's RegUnit tracking to be based on ↵Owen Anderson2015-01-311-54/+29
| | | | | | | | bit vectors. This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case. llvm-svn: 227678
* Change a very hot piece of code in TableGen's register unit computations to ↵Owen Anderson2015-01-301-1/+14
| | | | | | | | | | | | | | | | use bit vectors rather than arrays. For target descriptions with very large and very dense register files, TableGen can take an extremely long time to run. This change makes a dent in that (~15% in my measurements) by accelerating the single hottest operation with better data structures. I believe there's still a lot of room to make this even faster with more global changes that require replacing some of the existing datastructures in this area with bit vectors, but that's a more involved change and I wanted to get this simpler improvement in first. llvm-svn: 227562
* Clean up static analyzer warnings.Michael Ilseman2014-12-121-0/+1
| | | | | | | | | Clang's static analyzer found several potential cases of undefined behavior, use of un-initialized values, and potentially null pointer dereferences in tablegen, Support, MC, and ADT. This cleans them up with specific assertions on the assumptions of the code. llvm-svn: 224154
* Tablegen'erate lanemasks for register units.Matthias Braun2014-12-101-0/+37
| | | | | | Now we can relate lanemasks in a virtual register to register units. llvm-svn: 223889
* Add function that translates subregister lane masks to other subregs.Matthias Braun2014-12-101-0/+64
| | | | | | | This works like the composeSubRegisterIndices() function but transforms a subregister lane mask instead of a subregister index. llvm-svn: 223874
* Let tablegen compute maximum lanemask for regs/regclasses.Matthias Braun2014-12-101-3/+15
| | | | | | | | Let tablegen compute the combination of subregister lanemasks for all subregisters in a register/register class. This is preparation for further work subregister allocation llvm-svn: 223873
* range-for some thingsDavid Blaikie2014-12-031-19/+12
| | | | llvm-svn: 223263
* Simplify CodeGenRegBank::inferMatchingSuperRegClass & its caller by passing ↵David Blaikie2014-12-031-16/+16
| | | | | | an iterator rather than index llvm-svn: 223262
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-57/+59
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-58/+66
| | | | | | range-for isn't suitable. llvm-svn: 223260
* Remove some unnecessary vector::reserve/assign calls.David Blaikie2014-11-291-9/+5
| | | | llvm-svn: 222959
* Remove indirection of vector<T*> in favor of deque<T>David Blaikie2014-11-291-36/+32
| | | | llvm-svn: 222958
* Use deque<T> rather than vector<T*> since it provides the same invalidation ↵David Blaikie2014-11-291-27/+19
| | | | | | | | | | | | | | | semantics (at least when removal is not needed) without the extra indirection/ownership complexity Order matters for this container, it seems (using a forward_list and replacing the original push_backs with emplace_fronts caused test failures). I didn't look too deeply into why. (& in retrospect, I might go back & change some of the forward_lists I introduced to deques anyway - since most don't require removal, deque is a more memory-friendly data structure (moderate locality while not invalidating pointers)) llvm-svn: 222950
* Constify some things in preparation for CodeGenSubRegIndex to be stored by ↵David Blaikie2014-11-291-22/+21
| | | | | | value in their container, removing the indirection llvm-svn: 222949
* Fix a few memory leaks in CodeGenRegBank.Craig Topper2014-11-281-0/+6
| | | | llvm-svn: 222930
* Remove StringMap::GetOrCreateValue in favor of StringMap::insertDavid Blaikie2014-11-191-3/+6
| | | | | | | | | | | | | | Having two ways to do this doesn't seem terribly helpful and consistently using the insert version (which we already has) seems like it'll make the code easier to understand to anyone working with standard data structures. (I also updated many references to the Entry's key and value to use first() and second instead of getKey{Data,Length,} and get/setValue - for similar consistency) Also removes the GetOrCreateValue functions so there's less surface area to StringMap to fix/improve/change/accommodate move semantics, etc. llvm-svn: 222319
* Fix some cases were ArrayRefs were being passed by reference. Also remove ↵Craig Topper2014-08-271-1/+1
| | | | | | 'const' from some other ArrayRef uses since its implicitly const already. llvm-svn: 216524
* Use range based for loops to avoid needing to re-mention SmallPtrSet size.Craig Topper2014-08-241-3/+2
| | | | llvm-svn: 216351
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | definition below all of the header #include lines, TableGen edition. llvm-svn: 206846
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-151-6/+6
| | | | | | instead of comparing to nullptr. llvm-svn: 206254
* tblgen: Twinify PrintFatalError.Benjamin Kramer2014-03-291-1/+1
| | | | | | No functionality change. llvm-svn: 205110
* [C++11] Add 'override' keywords to tablegen code.Craig Topper2014-03-051-1/+1
| | | | llvm-svn: 202937
* [C++11] Use std::tie to simplify compare operators.Benjamin Kramer2014-03-031-5/+2
| | | | | | No functionality change. llvm-svn: 202751
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
| | | | | | Remove the old functions. llvm-svn: 202636
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-11/+4
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to ↵Craig Topper2014-01-241-1/+1
| | | | | | facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before). llvm-svn: 200036
* Provide basic type safety for array_pod_sort comparators.Benjamin Kramer2013-09-221-3/+4
| | | | | | | | This makes using array_pod_sort significantly safer. The implementation relies on function pointer casting but that should be safe as we're dealing with void* here. llvm-svn: 191175
* comment typo.Andrew Trick2013-07-311-1/+1
| | | | llvm-svn: 187531
* Fix register pressure tables on ARM.Andrew Trick2013-07-311-3/+31
| | | | | | The heuristic that merges register pressure sets was bogus for ARM's S/D regs. llvm-svn: 187479
* Add tracing to the tblgen register pressure table generator.Andrew Trick2013-07-311-7/+63
| | | | llvm-svn: 187478
* RegPressure: Order the "pressure sets" by number of regunits per set.Andrew Trick2013-07-251-1/+26
| | | | | | This lets heuristics easily pick the most important set to follow. llvm-svn: 187108
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-1/+1
| | | | | | size. llvm-svn: 186274
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-271-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 llvm-svn: 185094
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-1/+14
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-311-3/+5
| | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-281-49/+0
| | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 llvm-svn: 182783
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-161-5/+23
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
* [TableGen] Fix ICE on MSVC 2012 Release builds.Michael J. Spencer2013-02-261-1/+3
| | | | llvm-svn: 176125
* Clarify intent.Jakob Stoklund Olesen2013-01-311-0/+6
| | | | llvm-svn: 174068
* TableGen: Keep track of superclass reference ranges.Jordan Rose2013-01-101-2/+4
| | | | | | | | | | def foo : bar; ~~~ This allows us to produce more precise diagnostics about a certain superclass, and even provide fixits. llvm-svn: 172085
* RegisterPressure API. Add support for physical register units.Andrew Trick2012-12-051-0/+29
| | | | | | | | | | | | | At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. llvm-svn: 169360
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-19/+21
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Don't use stack unwinding to provide the location information forJoerg Sonnenberger2012-10-241-2/+2
| | | | | | SetTheory, but pass down the location explicitly. llvm-svn: 166629
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-271-1/+1
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
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