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path: root/llvm/utils/TableGen/CodeGenRegisters.cpp
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* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-271-1/+1
| | | | llvm-svn: 164767
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-111-0/+6
| | | | | | list of registers every time we want to look up a register by name. llvm-svn: 163659
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-2/+49
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Clean the sub-reg index composition maps at emission.Jakob Stoklund Olesen2012-09-111-15/+0
| | | | | | | Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. llvm-svn: 163629
* Print out the location of expanded multiclass defs in TableGen errors.Jakob Stoklund Olesen2012-08-221-2/+2
| | | | | | | | | | | | | | | | | | | When reporting an error for a defm, we would previously only report the location of the outer defm, which is not always where the error is. Now we also print the location of the expanded multiclass defs: lib/Target/X86/X86InstrSSE.td:2902:12: error: foo defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>, ^ lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128, ^ lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), ^ llvm-svn: 162409
* Add a CoveringSubRegIndices field to SubRegIndex records.Jakob Stoklund Olesen2012-08-151-9/+22
| | | | | | | This can be used to tell TableGen to use a specific SubRegIndex instead of synthesizing one when discovering all sub-registers. llvm-svn: 161982
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-151-15/+21
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. llvm-svn: 161964
* Remove support for 'CompositeIndices' and sub-register cycles.Jakob Stoklund Olesen2012-07-261-52/+19
| | | | | | | | | | | | Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone, there is no longer a need for the CompositeIndices construct in .td files. Sub-register index composition can be specified on the SubRegIndex itself using the ComposedOf field. Also enforce unique names for sub-registers in TableGen. The same sub-register cannot be available with multiple sub-register indexes. llvm-svn: 160842
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-021-3/+3
| | | | llvm-svn: 157885
* Emit register unit lists for each register.Jakob Stoklund Olesen2012-05-291-0/+5
| | | | | | | | | | | | | | | | Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. llvm-svn: 157650
* Also compute TopoSigs in synthetic register classes.Jakob Stoklund Olesen2012-05-221-2/+7
| | | | | | | CodeGenRegisterClass has two constructors. Both need to compute the TopoSigs BitVector. llvm-svn: 157271
* Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen2012-05-161-71/+49
| | | | | | | | | | | TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. llvm-svn: 156960
* Create a struct representing register units in TableGen.Jakob Stoklund Olesen2012-05-151-18/+6
| | | | | | | | | | | | Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. llvm-svn: 156792
* Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen2012-05-141-12/+41
| | | | | | | | | | | | | | | | | | | | | | | Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. llvm-svn: 156763
* Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen2012-05-141-5/+11
| | | | | | | | | | | | | The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). llvm-svn: 156762
* Compute topological signatures of registers.Jakob Stoklund Olesen2012-05-141-6/+36
| | | | | | | | | | | | | | | TableGen creates new register classes and sub-register indices based on the sub-register structure present in the register bank. So far, it has been doing that on a per-register basis, but that is not very efficient. This patch teaches TableGen to compute topological signatures for registers, and use that to reduce the amount of redundant computation. Registers get the same TopoSig if they have identical sub-register structure. TopoSigs are not currently exposed outside TableGen. llvm-svn: 156761
* Speed up computeComposites() by using the new SubReg -> SubIdx map.Jakob Stoklund Olesen2012-05-121-12/+10
| | | | | | | TableGen doesn't need to search through the SubRegs map to find an inverse entry. llvm-svn: 156690
* Remove extraneous ; and the resulting warning.Bill Wendling2012-05-111-1/+1
| | | | llvm-svn: 156649
* Defer computation of SuperRegs.Jakob Stoklund Olesen2012-05-111-11/+31
| | | | | | | | Don't compute the SuperRegs list until the sub-register graph is completely finished. This guarantees that the list of super-registers is properly topologically ordered, and has no duplicates. llvm-svn: 156629
* Compute secondary sub-registers.Jakob Stoklund Olesen2012-05-101-0/+136
| | | | | | | | | | | | | | | | | | | | | | The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. llvm-svn: 156587
* Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen2012-05-101-19/+29
| | | | | | | | The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. llvm-svn: 156555
* Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick2012-05-101-4/+9
| | | | | | I initially assumed that the subreg graph was a tree. That may not be true. llvm-svn: 156524
* Fix warning text.Jakob Stoklund Olesen2012-05-091-1/+1
| | | | llvm-svn: 156521
* Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen2012-05-091-0/+16
| | | | | | | | | | | | | | | | This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. llvm-svn: 156519
* Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen2012-05-091-8/+9
| | | | | | That's what it does. llvm-svn: 156518
* Order register classes by spill size first, members last.Jakob Stoklund Olesen2012-05-041-7/+7
| | | | | | | | | | | | This is still a topological ordering such that every register class gets a smaller enum value than its sub-classes. Placing the smaller spill sizes first makes a difference for the super-register class bit masks. When looking for a super-register class, we usually want the smallest possible kind of super-register. That is now available as the first bit set in the bit mask. llvm-svn: 156222
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-041-23/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* tblgen: remove duplicated newlines.Benjamin Kramer2012-04-181-1/+1
| | | | llvm-svn: 155038
* Move a few more warnings to use PrintWarning().Jim Grosbach2012-04-181-5/+5
| | | | llvm-svn: 155027
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-111-13/+12
| | | | llvm-svn: 154518
* TableGen'd regpressure: register unit set pruning.Andrew Trick2012-04-111-18/+14
| | | | | | | The pruning is more complete if it is not done incrementally. The code is also a tad less convluted. llvm-svn: 154510
* Table-generated register pressure fixes.Andrew Trick2012-04-111-24/+47
| | | | | | | Handle mixing allocatable and unallocatable register gracefully. Simplify the pruning of register unit sets. llvm-svn: 154474
* TableGen/reginfo potential bug: typo from previous checkin.Andrew Trick2012-04-101-1/+1
| | | | llvm-svn: 154452
* Fix for register pressure tables.Andrew Trick2012-04-101-13/+15
| | | | | | Recent refactoring introduced a bug. Fix: added buildRegUnitSets. llvm-svn: 154382
* Use std::includes instead of my own implementation.Andrew Trick2012-04-101-9/+2
| | | | | | Jakob's review. llvm-svn: 154377
* Added register unit sets to the target description.Andrew Trick2012-04-101-0/+167
| | | | | | | | | | This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. llvm-svn: 154374
* Added register unit weights to the target description.Andrew Trick2012-04-101-17/+306
| | | | | | | | | | | | This is a new algorithm that associates registers with weighted register units to accuretely model their effect on register pressure. This handles registers with multiple overlapping subregisters. It is possible, but almost inconceivable that the algorithm fails to find an exact solution for a target description. If an exact solution cannot be found, an inexact, but reasonable solution will be chosen. llvm-svn: 154373
* Cleanup set_union usage. The same thing but a bit cleaner now.Andrew Trick2012-04-031-1/+1
| | | | llvm-svn: 153922
* Use std::set_union instead of nasty custom code.Andrew Trick2012-04-031-13/+3
| | | | | | | I just noticed Jakob's examples of the proper application of std::set... routines. llvm-svn: 153918
* comment typoAndrew Trick2012-03-311-1/+1
| | | | llvm-svn: 153796
* Introduce Register Units: Give each leaf register a number.Andrew Trick2012-03-311-0/+49
| | | | | | | | First small step toward modeling multi-register multi-pressure. In the future, register units can also be used to model liveness and aliasing. llvm-svn: 153794
* Add more constness to CodeGenRegisters.Jakob Stoklund Olesen2012-03-291-3/+3
| | | | llvm-svn: 153667
* Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen2012-02-011-25/+74
| | | | | | | | | | | | | | | | | It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. llvm-svn: 149556
* Fix a bug in the TopoOrderRC comparison function.Jakob Stoklund Olesen2012-02-011-1/+1
| | | | | | | | | | | The final tie breaker comparison also needs to return +/-1, or 0. This is not a less() function. This could cause otherwise identical super-classes to be ordered unstably, depending on what the system qsort routine does with a bad compare function. llvm-svn: 149549
* Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen2012-01-311-20/+21
| | | | | | Each SubRegIndex keeps track of how it composes. llvm-svn: 149423
* Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen2012-01-311-37/+80
| | | | | | | | | This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. llvm-svn: 149418
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-12/+40
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
* Add TableGen support for callee saved registers.Jakob Stoklund Olesen2012-01-171-0/+23
| | | | | | | | | Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). llvm-svn: 148346
* Skip the NAME field when forming tuples.Jakob Stoklund Olesen2012-01-131-0/+3
| | | | llvm-svn: 148147
* Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen2012-01-131-1/+1
| | | | | | | The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. llvm-svn: 148092
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