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path: root/llvm/utils/TableGen/CodeGenInstruction.h
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* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-061-1/+5
| | | | | | getName() accessor. llvm-svn: 45645
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-0/+2
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | llvm-svn: 44969
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* No need for noResults anymore.Evan Cheng2007-07-201-1/+0
| | | | llvm-svn: 40075
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-0/+4
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-101-1/+1
| | | | llvm-svn: 38498
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-061-0/+1
| | | | | | are used to predicate instructions. llvm-svn: 37465
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-1/+1
| | | | | | without having a PredicateOperand. llvm-svn: 37116
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35159
* Remove the isTwoAddress property from the CodeGenInstruction class. It shouldChris Lattner2006-11-151-1/+24
| | | | | | | | | | not be used for anything other than backwards compat constraint handling. Add support for a new DisableEncoding property which contains a list of registers that should not be encoded by the generated code emitter. Convert the codeemitter generator to use this, fixing some PPC JIT regressions. llvm-svn: 31769
* ADd support for adding constraints to suboperandsChris Lattner2006-11-151-2/+18
| | | | llvm-svn: 31748
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-8/+3
| | | | | | to extend. llvm-svn: 31481
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-061-0/+1
| | | | llvm-svn: 31480
* Unbreak VC++ build.Jeff Cohen2006-11-051-1/+2
| | | | llvm-svn: 31464
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-0/+8
| | | | llvm-svn: 31333
* * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag andEvan Cheng2006-01-091-2/+0
| | | | | | | | | SNDPOutFlag to DAG nodes. These properties do not belong to target specific instructions. * Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's optional. Used by ret / call, etc. llvm-svn: 25154
* Added field noResults to Instruction.Evan Cheng2005-12-261-0/+1
| | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. llvm-svn: 25017
* * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAGEvan Cheng2005-12-231-0/+2
| | | | | | | support which is fragile. * Fixed a number of bugs. llvm-svn: 24996
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-041-0/+1
| | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. llvm-svn: 24587
* Nuke CodeGenInstruction's ValueType member, it is no longer used.Nate Begeman2005-12-011-9/+3
| | | | llvm-svn: 24556
* fit into 80 columnsNate Begeman2005-11-301-2/+2
| | | | llvm-svn: 24554
* Teach tblgen about instruction operands that have multiple MachineInstrChris Lattner2005-11-191-2/+9
| | | | | | | operands, digging into them to find register values (used on X86). Patch by Evan Cheng! llvm-svn: 24424
* spell this variable rightChris Lattner2005-08-261-1/+1
| | | | llvm-svn: 23095
* Expose a new flag to TargetInstrInfoChris Lattner2005-08-261-0/+1
| | | | llvm-svn: 23094
* For now, just emit empty operand info structures.Chris Lattner2005-08-191-0/+1
| | | | llvm-svn: 22910
* Figure out how many operands each instruction has, keep track of whetherChris Lattner2005-08-181-2/+5
| | | | | | or not it's variable. llvm-svn: 22885
* Remove trailing whitespaceMisha Brukman2005-04-221-3/+3
| | | | llvm-svn: 21428
* Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.Chris Lattner2005-01-021-0/+2
| | | | llvm-svn: 19243
* Add support for the isLoad and isStore flags, needed by the instruction ↵Nate Begeman2004-09-281-0/+2
| | | | | | scheduler llvm-svn: 16554
* Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAGChris Lattner2004-09-281-0/+1
| | | | llvm-svn: 16553
* Make the AsmWriter a first-class tblgen object. Allow targets to specifyChris Lattner2004-08-141-1/+1
| | | | | | name of the generated asmwriter class, and the name of the format string. llvm-svn: 15747
* Start parsing more information from the Operand informationChris Lattner2004-08-111-5/+25
| | | | llvm-svn: 15644
* Parse the operand list of the instruction. We currently support register ↵Chris Lattner2004-08-011-1/+18
| | | | | | and immediate operands. llvm-svn: 15390
* Add, and start using, the CodeGenInstruction class. This class representsChris Lattner2004-08-011-0/+49
an instance of the Instruction tablegen class. llvm-svn: 15385
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