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path: root/llvm/utils/TableGen/CodeGenInstruction.h
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* move FlattenVariants out of AsmMatcherEmitter into a sharedChris Lattner2010-11-011-0/+7
| | | | | | | | CodeGenInstruction::FlattenAsmStringVariants method. Use it to simplify the code in AsmWriterInst, which now no longer needs to worry about variants. llvm-svn: 117886
* Allow targets to optionally specify custom binary encoder functions forJim Grosbach2010-10-121-3/+8
| | | | | | | | operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. llvm-svn: 116353
* When figuring out which operands match which encoding fields in an instruction,Jim Grosbach2010-10-111-0/+5
| | | | | | | try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). llvm-svn: 116211
* trailing whitespaceJim Grosbach2010-10-081-15/+15
| | | | llvm-svn: 116068
* Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson2010-09-231-1/+0
| | | | | | | | instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! llvm-svn: 114710
* Add an TargetInstrDesc bit to indicate that a given instruction is a ↵Owen Anderson2010-09-231-0/+1
| | | | | | | | conditional move. Not intended functionality change, as nothing uses this yet. llvm-svn: 114702
* Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling2010-08-081-0/+1
| | | | | | useful after all. llvm-svn: 110531
* Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling2010-08-061-1/+0
| | | | | | | | | | | | | need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h llvm-svn: 110424
* Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling2010-07-301-0/+1
| | | | | | | later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. llvm-svn: 109901
* hoist some funky logic into CodeGenInstructionChris Lattner2010-03-271-0/+7
| | | | | | | | | from two places in CodeGenDAGPatterns.cpp, and use it in DAGISelMatcherGen.cpp instead of using an incorrect predicate that happened to get lucky on our current targets. llvm-svn: 99726
* capture implicit uses and defs in CodeGenInstructionChris Lattner2010-03-181-0/+4
| | | | llvm-svn: 98879
* remove some code that was working around old sparc v9 backend bugs.Chris Lattner2010-03-181-1/+2
| | | | | | Add checking that the input/output operand list in spelled right. llvm-svn: 98865
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-271-1/+0
| | | | llvm-svn: 97348
* work around a gcc bug with -Wuninitialized.Chris Lattner2010-02-101-0/+1
| | | | llvm-svn: 95808
* Introduce a new CodeGenInstruction::ConstraintInfo classChris Lattner2010-02-101-1/+30
| | | | | | | | | for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). llvm-svn: 95753
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-1/+1
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng2009-10-011-0/+2
| | | | | | | | | | set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. llvm-svn: 83196
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-1/+1
| | | | llvm-svn: 60487
* Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling2008-05-281-1/+4
| | | | | | | | | instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. llvm-svn: 51660
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
| | | | llvm-svn: 48381
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-2/+1
| | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. llvm-svn: 45829
* add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner2008-01-081-1/+1
| | | | | | This is currently not set by anything. llvm-svn: 45748
* rename hasVariableOperands() -> isVariadic(). Add some comments.Chris Lattner2008-01-071-1/+1
| | | | | | | Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. llvm-svn: 45687
* the name field of instructions is never set to a non-empty string, Chris Lattner2008-01-071-5/+0
| | | | | | just unconditionally use the def name of the instruction. llvm-svn: 45684
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-061-1/+5
| | | | | | getName() accessor. llvm-svn: 45645
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45419
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-0/+2
| | | | | | side effects for machine instructions. llvm-svn: 45022
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | llvm-svn: 44969
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* No need for noResults anymore.Evan Cheng2007-07-201-1/+0
| | | | llvm-svn: 40075
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-0/+4
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-101-1/+1
| | | | llvm-svn: 38498
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | llvm-svn: 37643
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-061-0/+1
| | | | | | are used to predicate instructions. llvm-svn: 37465
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-1/+1
| | | | | | without having a PredicateOperand. llvm-svn: 37116
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35159
* Remove the isTwoAddress property from the CodeGenInstruction class. It shouldChris Lattner2006-11-151-1/+24
| | | | | | | | | | not be used for anything other than backwards compat constraint handling. Add support for a new DisableEncoding property which contains a list of registers that should not be encoded by the generated code emitter. Convert the codeemitter generator to use this, fixing some PPC JIT regressions. llvm-svn: 31769
* ADd support for adding constraints to suboperandsChris Lattner2006-11-151-2/+18
| | | | llvm-svn: 31748
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-8/+3
| | | | | | to extend. llvm-svn: 31481
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-061-0/+1
| | | | llvm-svn: 31480
* Unbreak VC++ build.Jeff Cohen2006-11-051-1/+2
| | | | llvm-svn: 31464
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-0/+8
| | | | llvm-svn: 31333
* * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag andEvan Cheng2006-01-091-2/+0
| | | | | | | | | SNDPOutFlag to DAG nodes. These properties do not belong to target specific instructions. * Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's optional. Used by ret / call, etc. llvm-svn: 25154
* Added field noResults to Instruction.Evan Cheng2005-12-261-0/+1
| | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. llvm-svn: 25017
* * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAGEvan Cheng2005-12-231-0/+2
| | | | | | | support which is fragile. * Fixed a number of bugs. llvm-svn: 24996
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-041-0/+1
| | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. llvm-svn: 24587
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