| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | simplify the way operand flags and constraints are handled, making it easier | Chris Lattner | 2006-11-06 | 1 | -8/+3 | |
| | | | | | | | to extend. llvm-svn: 31481 | |||||
| * | recognize ppc's blr instruction as predicated | Chris Lattner | 2006-11-06 | 1 | -0/+1 | |
| | | | | | llvm-svn: 31480 | |||||
| * | Unbreak VC++ build. | Jeff Cohen | 2006-11-05 | 1 | -1/+2 | |
| | | | | | llvm-svn: 31464 | |||||
| * | Add operand constraints to TargetInstrInfo. | Evan Cheng | 2006-11-01 | 1 | -0/+8 | |
| | | | | | llvm-svn: 31333 | |||||
| * | * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and | Evan Cheng | 2006-01-09 | 1 | -2/+0 | |
| | | | | | | | | | | SNDPOutFlag to DAG nodes. These properties do not belong to target specific instructions. * Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's optional. Used by ret / call, etc. llvm-svn: 25154 | |||||
| * | Added field noResults to Instruction. | Evan Cheng | 2005-12-26 | 1 | -0/+1 | |
| | | | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. llvm-svn: 25017 | |||||
| * | * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG | Evan Cheng | 2005-12-23 | 1 | -0/+2 | |
| | | | | | | | | support which is fragile. * Fixed a number of bugs. llvm-svn: 24996 | |||||
| * | * Commit the fix (by Chris) for a tblgen type inferencing bug. | Evan Cheng | 2005-12-04 | 1 | -0/+1 | |
| | | | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. llvm-svn: 24587 | |||||
| * | Nuke CodeGenInstruction's ValueType member, it is no longer used. | Nate Begeman | 2005-12-01 | 1 | -9/+3 | |
| | | | | | llvm-svn: 24556 | |||||
| * | fit into 80 columns | Nate Begeman | 2005-11-30 | 1 | -2/+2 | |
| | | | | | llvm-svn: 24554 | |||||
| * | Teach tblgen about instruction operands that have multiple MachineInstr | Chris Lattner | 2005-11-19 | 1 | -2/+9 | |
| | | | | | | | | operands, digging into them to find register values (used on X86). Patch by Evan Cheng! llvm-svn: 24424 | |||||
| * | spell this variable right | Chris Lattner | 2005-08-26 | 1 | -1/+1 | |
| | | | | | llvm-svn: 23095 | |||||
| * | Expose a new flag to TargetInstrInfo | Chris Lattner | 2005-08-26 | 1 | -0/+1 | |
| | | | | | llvm-svn: 23094 | |||||
| * | For now, just emit empty operand info structures. | Chris Lattner | 2005-08-19 | 1 | -0/+1 | |
| | | | | | llvm-svn: 22910 | |||||
| * | Figure out how many operands each instruction has, keep track of whether | Chris Lattner | 2005-08-18 | 1 | -2/+5 | |
| | | | | | | | or not it's variable. llvm-svn: 22885 | |||||
| * | Remove trailing whitespace | Misha Brukman | 2005-04-22 | 1 | -3/+3 | |
| | | | | | llvm-svn: 21428 | |||||
| * | Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. | Chris Lattner | 2005-01-02 | 1 | -0/+2 | |
| | | | | | llvm-svn: 19243 | |||||
| * | Add support for the isLoad and isStore flags, needed by the instruction ↵ | Nate Begeman | 2004-09-28 | 1 | -0/+2 | |
| | | | | | | | scheduler llvm-svn: 16554 | |||||
| * | Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG | Chris Lattner | 2004-09-28 | 1 | -0/+1 | |
| | | | | | llvm-svn: 16553 | |||||
| * | Make the AsmWriter a first-class tblgen object. Allow targets to specify | Chris Lattner | 2004-08-14 | 1 | -1/+1 | |
| | | | | | | | name of the generated asmwriter class, and the name of the format string. llvm-svn: 15747 | |||||
| * | Start parsing more information from the Operand information | Chris Lattner | 2004-08-11 | 1 | -5/+25 | |
| | | | | | llvm-svn: 15644 | |||||
| * | Parse the operand list of the instruction. We currently support register ↵ | Chris Lattner | 2004-08-01 | 1 | -1/+18 | |
| | | | | | | | and immediate operands. llvm-svn: 15390 | |||||
| * | Add, and start using, the CodeGenInstruction class. This class represents | Chris Lattner | 2004-08-01 | 1 | -0/+49 | |
| an instance of the Instruction tablegen class. llvm-svn: 15385 | ||||||
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