summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Revert r334764, as it breaks some botsFlorian Hahn2018-06-141-236/+236
| | | | llvm-svn: 334767
* [TableGen] Make TreePatternNode::getChild return a reference (NFC)Florian Hahn2018-06-141-236/+236
| | | | | | | | The return value of TreePatternNode::getChild is never null. This patch also updates various places that use return values of getChild to also use references. Those changes were suggested post-commit for D47463. llvm-svn: 334764
* [TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).Florian Hahn2018-06-141-21/+21
| | | | | | Those changes were suggested post-commit for D47463. llvm-svn: 334706
* [TableGen] Make getOnlyTree return a const ref (NFC)Florian Hahn2018-06-131-8/+10
| | | | | | | This avoids some unnecessary copies of shared_ptrs. Those changes were suggested post-commit for D47463. llvm-svn: 334656
* TableGen: Change some pointer parameters to references since they're never ↵David Blaikie2018-06-111-20/+21
| | | | | | null anyway llvm-svn: 334446
* [TableGen] Make better use of std::map::emplace and emplace construct the ↵Craig Topper2018-06-101-9/+10
| | | | | | object in the map rather than moving it into it. Remove a use std::map::find by remembering the return from emplace. llvm-svn: 334380
* Revert r334374 [TableGen] Move some shared_ptrs to avoid unnecessary copies ↵Florian Hahn2018-06-101-21/+20
| | | | | | | | (NFC). This breaks some builders. llvm-svn: 334376
* [TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).Florian Hahn2018-06-101-20/+21
| | | | | | Those changes were suggested post-commit for D47463. llvm-svn: 334374
* [TableGen] Make DAGInstruction own Pattern to avoid leaking it.Florian Hahn2018-06-081-7/+9
| | | | | | | | | | Reviewers: dsanders, craig.topper, stoklund, nhaehnle Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47525 llvm-svn: 334275
* TableGen/DAGPatterns: Allow bit constants in addition to int constantsNicolai Haehnle2018-06-041-3/+5
| | | | | | | | | | | | | | | Summary: Implicit casting is a simple quality of life improvement. Change-Id: I3d2b31b8b8f12cbb1e84f691e359fa713a9c4b42 Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D47432 llvm-svn: 333904
* [TableGen] Avoid leaking TreePatternNodes by using shared_ptr.Florian Hahn2018-05-301-172/+165
| | | | | | | | | | | | By using std::shared_ptr for TreePatternNode, we can avoid leaking them. Reviewers: craig.topper, dsanders, stoklund, tstellar, zturner Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D47463 llvm-svn: 333591
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-25/+23
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
* Fix a bunch of typoes. NFCFangrui Song2018-03-301-1/+1
| | | | llvm-svn: 328907
* [TableGen] Add support of Intrinsics with multiple returnsHal Finkel2018-01-031-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change deals with intrinsics with multiple outputs, for example load instrinsic with address updated. DAG selection for Instrinsics could be done either through source code or tablegen. Handling all intrinsics in source code would introduce a huge chunk of repetitive code if we have a large number of intrinsic that return multiple values (see NVPTX as an example). While intrinsic class in tablegen supports multiple outputs, tablegen only supports Intrinsics with zero or one output on TreePattern. This appears to be a simple bug in tablegen that is fixed by this change. For Intrinsics defined as: def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; Instruction will be defined as: def L32_X: Inst<(outs reg:$d1, reg:$d2), (ins reg:$s1, reg:$s2), "ld32_x $d1, $d2, $s2", [(set i32:$d1, i32:$d2, (int_xxx_load_addr_updated i32:$s1, i32:$s2))]>; Patch by Wenbo Sun, thanks! Differential Revision: https://reviews.llvm.org/D32888 llvm-svn: 321704
* Avoid int to string conversion in Twine or raw_ostream contexts.Benjamin Kramer2017-12-281-8/+7
| | | | | | Some output changes from uppercase hex to lowercase hex, no other functionality change intended. llvm-svn: 321526
* [TableGen] Print more helpful information in case of type contradictionKrzysztof Parzyszek2017-12-211-18/+31
| | | | | | Dump the failing TreePattern. llvm-svn: 321282
* TableGen: Allow setting SDNodeProperties on intrinsicsMatt Arsenault2017-12-201-33/+12
| | | | | | | | | | | | | | | | | Allows preserving MachineMemOperands on intrinsics through selection. For reasons I don't understand, this is a static property of the pattern and the selector deliberately goes out of its way to drop if not present. Intrinsics already inherit from SDPatternOperator allowing them to be used directly in instruction patterns. SDPatternOperator has a list of SDNodeProperty, but you currently can't set them on the intrinsic. Without SDNPMemOperand, when the node is selected any memory operands are always dropped. Allowing setting this on the intrinsics avoids needing to introduce another equivalent target node just to have SDNPMemOperand set. llvm-svn: 321212
* [globalisel][tablegen] Add support for relative AtomicOrderingsDaniel Sanders2017-11-301-1/+40
| | | | | | | No test yet because the relevant rules are blocked on the atomic_load, and atomic_store nodes. llvm-svn: 319475
* [tablegen] Handle atomic predicates for ordering inside tablegen. NFC.Daniel Sanders2017-11-131-1/+53
| | | | | | | | | | | | | | | | Similar to r315841, GlobalISel and SelectionDAG require different code for the common atomic predicates due to differences in the representation. Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common atomic predicates related to ordering into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. llvm-svn: 318102
* [tablegen] Handle atomic predicates for memory type inside tablegen. NFC.Daniel Sanders2017-11-131-12/+31
| | | | | | | | | | | | | | | | Similar to r315841, GlobalISel and SelectionDAG require different code for the common atomic predicates due to differences in the representation. Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common atomic predicates related to memory type into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. llvm-svn: 318095
* [globalisel][tablegen] Import signextload and zeroextload.Daniel Sanders2017-11-111-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971
* [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish ↵Florian Hahn2017-11-071-0/+5
| | | | | | | | | | | | | | | Scalable Vectors Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 llvm-svn: 317564
* [tablegen] Use hasPredCode()/hasImmCode() instead of ↵Daniel Sanders2017-10-151-4/+14
| | | | | | | | getPredCode().empty()/getImmCode().empty(). NFC These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty. llvm-svn: 315872
* [TableGen] Remove error checks incorrectly failing on non-error conditionsKrzysztof Parzyszek2017-10-151-49/+6
| | | | | | | | | | | | | In type inference, an empty type set for a specific hw mode is not an error. In earlier stages of the design it was, but having to use non- parameterized types with target intrinsics necessarily led to type contradictions: since the intrinsics used specific types, they were only valid for a specific hw mode, and the resulting type set for other modes ended up empty. To accommodate the existence of such intrinsics individual type sets were allowed to be empty as long as not all sets were empty. llvm-svn: 315858
* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-151-7/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-141-10/+10
| | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters. llvm-svn: 315826
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 ↵Daniel Sanders2017-10-131-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use them. Summary: The purpose of this patch is to expose more information about ImmLeaf-like PatLeaf's so that GlobalISel can learn to import them. Previously, ImmLeaf could only be used to test int64_t's produced by sign-extending an APInt. Other tests on immediates had to use the generic PatLeaf and extract the constant using C++. With this patch, tablegen will know how to generate predicates for APInt, and APFloat. This will allow it to 'do the right thing' for both SelectionDAG and GlobalISel which require different methods of extracting the immediate from the IR. This is NFC for SelectionDAG since the new code is equivalent to the previous code. It's also NFC for FastISel because FastIselShouldIgnore is 1 for the ImmLeaf subclasses. Enabling FastIselShouldIgnore == 0 for these new subclasses will require a significant re-factor of FastISel. For GlobalISel, it's currently NFC because the relevant code to import the affected rules is not yet present. This will be added in a later patch. Depends on D36086 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: bjope, aemerson, rengolin, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36534 llvm-svn: 315747
* Revert r315148 [TableGen] Avoid unnecessary std::string creationsDaniel Sanders2017-10-131-8/+8
| | | | | | | | I'm about to commit a patch that makes them necessary for getPredCode() and it would be strange for getPredCode() and getImmCode() to require different usage. llvm-svn: 315733
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-071-8/+8
| | | | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters and in CodeGenDAGPatterns::getSDNodeNamed Differential Revision: https://reviews.llvm.org/D38624 llvm-svn: 315148
* Use const where possible. NFCI.Simon Pilgrim2017-09-271-1/+1
| | | | llvm-svn: 314292
* Tidyup P->getComplexPatternInfo call by moving it inside if( != NULL) test. ↵Simon Pilgrim2017-09-261-3/+1
| | | | | | NFCI. llvm-svn: 314202
* [TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek2017-09-221-2/+8
| | | | | | | | | | Also add operator<< for use with raw_ostream to InfoByHwMode and its derived classes. Recommitting r313989 with the fix for unresolved references: explicitly define the operator<< in namespace llvm. llvm-svn: 314004
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-09-221-2/+2
| | | | llvm-svn: 313996
* Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"Krzysztof Parzyszek2017-09-221-6/+2
| | | | | | This reverts commit r313989: it breaks Windows bots. llvm-svn: 313990
* [TableGen] Replace InfoByHwMode::getAsString with writeToStreamKrzysztof Parzyszek2017-09-221-2/+6
| | | | | | | Also add operator<< for use with raw_ostream to InfoByHwMode and its derived classes. llvm-svn: 313989
* [TableGen] Include StringMap.h instead of StringSet.h since that's the data ↵Craig Topper2017-09-211-1/+1
| | | | | | structure we use. llvm-svn: 313859
* [TableGen] Some optimizations to TableGen.Zachary Turner2017-09-201-39/+46
| | | | | | | | | This changes some STL data types to corresponding LLVM data types that have better performance characteristics. Differential Revision: https://reviews.llvm.org/D37957 llvm-svn: 313783
* Recommit r313647 now that GCC seems to accept the offeringKrzysztof Parzyszek2017-09-191-28/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some member types to MachineValueTypeSet::const_iterator so that iterator_traits can work with it. Improve TableGen performance of -gen-dag-isel (motivated by X86 backend) The introduction of parameterized register classes in r313271 caused the matcher generation code in TableGen to run much slower, particularly so in the unoptimized (debug) build. This patch recovers some of the lost performance. Summary of changes: - Cache the set of legal types in TypeInfer::getLegalTypes. The contents of this set do not change. - Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally this would not be necessary, but in the debug build TableGen is not optimized, so this helps a little bit. - Add an early exit from TypeSetByHwMode::operator== for the case when one or both arguments are "simple", i.e. only have one mode. This saves some time in GenerateVariants. - Finally, replace the underlying storage type in TypeSetByHwMode::SetType with MachineValueTypeSet based on std::array instead of std::set. This significantly reduces the number of memory allocation calls. I've done a number of experiments with the underlying type of InfoByHwMode. The type is a map, and for targets that do not use the parameterization, this map has only one entry. The best (unoptimized) performance, somewhat surprisingly came from std::map, followed closely by std::unordered_map. DenseMap was the slowest by a large margin. Various hand-crafted solutions (emulating enough of the map interface not to make sweeping changes to the users) did not yield any observable improvements. llvm-svn: 313660
* Revert "Improve TableGen performance of -gen-dag-isel (motivated by X86 ↵Krzysztof Parzyszek2017-09-191-52/+28
| | | | | | | | backend)" It breaks a lot of bots due to missing "__iterator_category". llvm-svn: 313651
* Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)Krzysztof Parzyszek2017-09-191-28/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The introduction of parameterized register classes in r313271 caused the matcher generation code in TableGen to run much slower, particularly so in the unoptimized (debug) build. This patch recovers some of the lost performance. Summary of changes: - Cache the set of legal types in TypeInfer::getLegalTypes. The contents of this set do not change. - Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally this would not be necessary, but in the debug build TableGen is not optimized, so this helps a little bit. - Add an early exit from TypeSetByHwMode::operator== for the case when one or both arguments are "simple", i.e. only have one mode. This saves some time in GenerateVariants. - Finally, replace the underlying storage type in TypeSetByHwMode::SetType with MachineValueTypeSet based on std::array instead of std::set. This significantly reduces the number of memory allocation calls. I've done a number of experiments with the underlying type of InfoByHwMode. The type is a map, and for targets that do not use the parameterization, this map has only one entry. The best (unoptimized) performance, somewhat surprisingly came from std::map, followed closely by std::unordered_map. DenseMap was the slowest by a large margin. Various hand-crafted solutions (emulating enough of the map interface not to make sweeping changes to the users) did not yield any observable improvements. llvm-svn: 313647
* Remove uses of deprecated std::not1.Benjamin Kramer2017-09-171-3/+3
| | | | | | | Lambdas are slightly more verbose, but also more readable. No functionality change intended. llvm-svn: 313482
* Fix selecting legal types in TypeInfer::getLegalTypesKrzysztof Parzyszek2017-09-151-9/+3
| | | | | | Collect all legal types for all modes. llvm-svn: 313380
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-729/+1017
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* [tblgen] Remove uses of std::ptr_fun, it's removed in C++17.Benjamin Kramer2017-09-141-8/+5
| | | | | | No functionality change intended. llvm-svn: 313269
* Remove ancient, commented out code from TableGen, NFCKrzysztof Parzyszek2017-09-121-12/+0
| | | | | | These pieces were commented out in r98534 and r129691, i.e. 6+ years ago. llvm-svn: 313038
* Formatting changes, add LLVM_DUMP_METHOD to a dump function, NFCKrzysztof Parzyszek2017-09-121-5/+4
| | | | llvm-svn: 313037
* [TableGen] Teach tablegen to allow SDNPCommutable nodes with more than 2 ↵Craig Topper2017-09-041-4/+9
| | | | | | | | | | | | | | | | | | | operands. Summary: Tablegen already supports commutable instrinsics with more than 2 operands. There it just assumes the first two operands are commutable. I plan to use this to improve the generation of FMA patterns in the X86 backend. Reviewers: aymanmus, zvi, RKSimon, spatel, arsenm Reviewed By: arsenm Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D37430 llvm-svn: 312464
* [TableGen] Fix a range based for loop to take the value by reference so that ↵Craig Topper2017-08-301-1/+1
| | | | | | SimplifyTree can modify the copy in the array if its needs to. llvm-svn: 312088
OpenPOWER on IntegriCloud