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* reduce indentation by eliminating 'else after return'Chris Lattner2010-02-231-23/+33
| | | | llvm-svn: 96889
* reduce nesting.Chris Lattner2010-02-171-3/+7
| | | | llvm-svn: 96466
* constizeChris Lattner2010-02-141-2/+2
| | | | llvm-svn: 96199
* clean up a bunch of code, move some random predicatesChris Lattner2010-02-141-0/+51
| | | | | | on TreePatternNode to be methods on TreePatternNode. llvm-svn: 96197
* tidy upChris Lattner2010-02-141-2/+4
| | | | llvm-svn: 96186
* Use the 'MadeChange' variable instead of returning 'false' all of the time.Bill Wendling2009-12-251-3/+2
| | | | llvm-svn: 92155
* Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this ↵Anton Korobeynikov2009-11-021-1/+0
| | | | | | | won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. PS: It seems that blackfin usage of copy_to_regclass is completely bogus! llvm-svn: 85766
* PR4795: Remove EEVT::isFP, isInt and isVec types used by TableGen's typeBob Wilson2009-08-291-28/+39
| | | | | | | | | | | | | | | inferencing. As far as I can tell, these are equivalent to the existing MVT::fAny, iAny and vAny types, and having both of them makes it harder to reason about and modify the type inferencing code. The specific problem in PR4795 occurs when updating a vAny type to be fAny or iAny, or vice versa. Both iAny and fAny include vector types -- they intersect with the set of types represented by vAny. When merging them, choose fAny/iAny to represent the intersection. This is not perfect, since fAny/iAny also include scalar types, but it is good enough for TableGen's type inferencing. llvm-svn: 80423
* Try to fix MSVC build after r79846.Benjamin Kramer2009-08-231-2/+3
| | | | llvm-svn: 79850
* Fix non-determinism in DAGISel emitter.Daniel Dunbar2009-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | - This manifested as non-determinism in the .inc output in rare cases (when two distinct patterns ended up being equivalent, which is rather rare). That meant the pattern matching was non-deterministic, which could eventually mean the code generator selected different instructions based on the arch. - It's probably worth making the DAGISel ensure a total ordering (or force the user to), but the simple fix here is to totally order the Record* maps based on a unique ID. - PR4672, PR4711. Yay: -- ddunbar@giles:~$ cat ~/llvm.obj.64/lib/Target/*/*.inc | shasum d1099ff34b21459a5a3e7021c225c080e6017ece - ddunbar@giles:~$ cat ~/llvm.obj.ppc/lib/Target/*/*.inc | shasum d1099ff34b21459a5a3e7021c225c080e6017ece - -- llvm-svn: 79846
* remove some DOUTsChris Lattner2009-08-231-15/+15
| | | | llvm-svn: 79821
* Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.Bob Wilson2009-08-121-6/+20
| | | | | | | | There have been a few times where I've wanted this but ended up leaving the operand type unconstrained. It is easy to add this now and should help catch errors in the future. llvm-svn: 78849
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-46/+46
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsicBob Wilson2009-08-111-2/+19
| | | | | | arguments that are vectors of any size and element type. llvm-svn: 78631
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-86/+86
| | | | | | own struct type. llvm-svn: 78610
* make ptr_rc derive from a new PointerLikeRegClass tblgen class.Chris Lattner2009-07-291-4/+4
| | | | llvm-svn: 77503
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-21/+21
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's ↵Evan Cheng2009-06-261-0/+4
| | | | | | looking for duplicates. llvm-svn: 74276
* Fix grammaro, and bad indentation.Nick Lewycky2009-06-171-3/+3
| | | | llvm-svn: 73602
* I'm going to assume that this was meant to be an assignment instead of aBill Wendling2009-06-091-1/+1
| | | | | | computation that isn't used. Please correct this if it's wrong! llvm-svn: 73139
* Revert 73074 and 73099 because Windows doesn't have POSIXDavid Greene2009-06-091-1/+1
| | | | | | | regular expressions. We will add an OpenBSD implementation and re-apply ASAP. llvm-svn: 73138
* Add a !patsubst operator. Use on string types.David Greene2009-06-081-1/+1
| | | | llvm-svn: 73099
* Make IntInits and ListInits typed. This helps deduce types of !if andDavid Greene2009-06-081-2/+21
| | | | | | | | other operators. For the rare cases where a list type cannot be deduced, provide a []<type> syntax, where <type> is the list element type. llvm-svn: 73078
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-021-13/+1
| | | | llvm-svn: 72712
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-011-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. llvm-svn: 72707
* 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.Nate Begeman2009-04-271-39/+2
| | | | | | | | | | | | | | PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. llvm-svn: 70225
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-241-4/+38
| | | | llvm-svn: 69967
* PR2957Nate Begeman2009-04-241-38/+4
| | | | | | | | | | | | | | ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. llvm-svn: 69952
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-1/+1
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-0/+6
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Tidy up some comments.Dan Gohman2009-03-311-3/+3
| | | | llvm-svn: 68112
* fix a few spelling errors and typosJim Grosbach2009-03-261-8/+8
| | | | llvm-svn: 67758
* Add support to tablegen for naming the nodes themselves, not just the operands, Nate Begeman2009-03-191-11/+11
| | | | | | | in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite, and as it turns out, cleans up a hack in the Alpha instruction info. llvm-svn: 67286
* add a new TGError class and use it to propagate location info withChris Lattner2009-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | errors when thrown. This gets us nice errors like this from tblgen: CMOVL32rr: (set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2)) /Users/sabre/llvm/Debug/bin/tblgen: error: Included from X86.td:116: Parsing X86InstrInfo.td:922: In CMOVL32rr: X86cmov node requires exactly 4 operands! def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 ^ instead of just: CMOVL32rr: (set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2)) /Users/sabre/llvm/Debug/bin/tblgen: In CMOVL32rr: X86cmov node requires exactly 4 operands! This is all I plan to do with this, but it should be easy enough to improve if anyone cares (e.g. keeping more loc info in "dag" expr records in tblgen. llvm-svn: 66898
* Reapply 63765. Patches for clang and llvm-gcc to follow.Dale Johannesen2009-02-051-1/+2
| | | | llvm-svn: 63812
* Reverting 63765. This broke the build of both clangDale Johannesen2009-02-041-2/+1
| | | | | | and llvm-gcc. llvm-svn: 63786
* New feature: add support for target intrinsics being defined in theNate Begeman2009-02-041-1/+2
| | | | | | | | | target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. llvm-svn: 63765
* Fix PR3453 and probably a bunch of other potentialDuncan Sands2009-02-011-1/+1
| | | | | | | | | crashes or wrong code with codegen of large integers: eliminate the legacy getIntegerVTBitMask and getIntegerVTSignBit methods, which returned their value as a uint64_t, so couldn't handle huge types. llvm-svn: 63494
* Handle iAny and fAny types in TreePatternNode::UpdateNodeType.Bob Wilson2009-01-051-5/+7
| | | | llvm-svn: 61713
* Fix spelling in some comments.Bob Wilson2009-01-051-1/+1
| | | | llvm-svn: 61702
* Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86'sDan Gohman2008-12-031-9/+0
| | | | | | | | | | | | foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-0/+9
| | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. llvm-svn: 60459
* Modify the intrinsics pattern to separate out the "return" types from theBill Wendling2008-11-131-8/+13
| | | | | | | | | | "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; llvm-svn: 59237
* Add support for having multiple predicates on a TreePatternNode.Dan Gohman2008-10-151-14/+33
| | | | | | | | This will allow predicates to be composed, which will allow the predicate definitions to become less redundant, and eventually will allow DAGISelEmitter.cpp to emit less redundant code. llvm-svn: 57562
* Factor out the predicate check code from DAGISelEmitter.cppDan Gohman2008-08-221-0/+27
| | | | | | | | | and use it in FastISelEmitter.cpp, and make FastISel subtarget aware. Among other things, this lets it work properly on x86 targets that don't have SSE, where it successfully selects x87 instructions. llvm-svn: 55156
* Added support for overloading intrinsics (atomics) based on pointersMon P Wang2008-07-301-5/+8
| | | | | | | to different address spaces. This alters the naming scheme for those intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32 llvm-svn: 54195
* check in anton's patch to make inlining happen in a determinstic orderChris Lattner2008-06-301-4/+6
| | | | | | | and fix the bug that it uncovers: inlining a pattern fragment could bring in other pattern fragments if the inlinee hadn't already been inlined. llvm-svn: 52888
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-0/+2
| | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub llvm-svn: 52706
* - Add "Commutative" property to intrinsics. This allows tblgen to generate ↵Evan Cheng2008-06-161-5/+31
| | | | | | | | the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. llvm-svn: 52353
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-74/+91
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
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