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path: root/llvm/utils/TableGen/CodeEmitterGen.cpp
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* Unconstify InitsDavid Greene2011-07-291-13/+13
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Create Inits Via Factory MethodDavid Greene2011-07-291-1/+1
| | | | | | | Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. llvm-svn: 136486
* [AVX] Constify InitsDavid Greene2011-07-291-13/+13
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* [AVX] Remove Mutating Members from InitsDavid Greene2011-07-291-4/+8
| | | | | | | Get rid of all Init members that modify internal state. This is in preparation for making references to Inits const. llvm-svn: 136483
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-22/+16
| | | | | | in multiple buildbots. llvm-svn: 134936
* Use get(0 Instead of Create()David Greene2011-07-111-1/+1
| | | | | | Respond to some feedback asking for a name change. llvm-svn: 134921
* [AVX] Make Inits FoldableDavid Greene2011-07-111-16/+22
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Don't require pseudo-instructions to carry encoding information.Jim Grosbach2011-07-061-3/+6
| | | | | | | | | | For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. llvm-svn: 134539
* Fix a bug in tblgen that caused incorrect encodings on instructions that ↵Owen Anderson2011-04-281-1/+5
| | | | | | | | | specified operands with "bit" instead of "bits<1>". Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> llvm-svn: 130410
* Tidy up a bit.Jim Grosbach2011-02-031-3/+3
| | | | llvm-svn: 124832
* Fix a comment typo.Bob Wilson2011-01-271-1/+1
| | | | llvm-svn: 124450
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-1/+1
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* Move <map> include out of .h and into .cpp.Bill Wendling2010-12-131-0/+1
| | | | llvm-svn: 121661
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-1/+1
| | | | llvm-svn: 121659
* pull the code to get the operand value out of the loop.Chris Lattner2010-11-151-48/+58
| | | | llvm-svn: 119130
* split the giant encoder loop into two new helper functions.Chris Lattner2010-11-151-112/+122
| | | | llvm-svn: 119129
* reduce nesting and minor cleanups, no functionality change.Chris Lattner2010-11-151-87/+88
| | | | llvm-svn: 119128
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-3/+3
| | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
* Add support for specifying a PostEncoderMethod, which can perform ↵Owen Anderson2010-11-111-0/+4
| | | | | | | | post-processing after the automated encoding of an instruction. Not yet used. llvm-svn: 118759
* Support generating an MC'ized CodeEmitter directly. Maintain a reference to theJim Grosbach2010-11-031-5/+18
| | | | | | | Fixups list for the instruction so the operand encoders can add to it as needed. llvm-svn: 118206
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-0/+6
| | | | | | assumptions about stack layout. Specifically, LR must be saved next to FP. llvm-svn: 118026
* Tidy up.Jim Grosbach2010-11-021-3/+0
| | | | llvm-svn: 117987
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-6/+7
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Allow targets to optionally specify custom binary encoder functions forJim Grosbach2010-10-121-5/+20
| | | | | | | | operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. llvm-svn: 116353
* The assert() should reference to machine instr operand number, too.Jim Grosbach2010-10-111-2/+2
| | | | llvm-svn: 116243
* Make sure to use the machine instruction operand number. It doesn't alwaysJim Grosbach2010-10-111-0/+2
| | | | | | map one-to-one with the CodeGenInstruction operand number. llvm-svn: 116238
* When figuring out which operands match which encoding fields in an instruction,Jim Grosbach2010-10-111-6/+17
| | | | | | | try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). llvm-svn: 116211
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116018
* trailing whitespaceJim Grosbach2010-10-071-17/+17
| | | | llvm-svn: 115923
* Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen2010-07-021-40/+5
| | | | | | | | | list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. llvm-svn: 107520
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-011-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 llvm-svn: 102815
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-1/+1
| | | | llvm-svn: 100709
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-3/+3
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* look up instructions by record, not by name.Chris Lattner2010-03-191-1/+1
| | | | llvm-svn: 98904
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-3/+3
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen2010-01-151-6/+3
| | | | | | Also, DEBUG_VALUE has side effects. llvm-svn: 93498
* Add DEBUG_DECLARE. Not used yet.Dale Johannesen2010-01-091-3/+6
| | | | llvm-svn: 93040
* Add DEBUG_VALUE. Not used yet.Dale Johannesen2010-01-081-3/+6
| | | | llvm-svn: 93030
* Revert 90628, which was incorrect.Dan Gohman2009-12-151-6/+9
| | | | llvm-svn: 91448
* Minor code simplification.Dan Gohman2009-12-051-9/+6
| | | | llvm-svn: 90628
* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-3/+3
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. llvm-svn: 83006
* Convert more abort() calls to llvm_report_error().Torok Edwin2009-07-081-2/+4
| | | | | | Also remove trailing semicolon. llvm-svn: 75027
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-1/+1
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-3/+3
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-5/+8
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Fix shift overflow bug that would occur when a field was a full 32-bits Chris Lattner2008-10-051-1/+1
| | | | | | | in tblgen. This is PR2827, thanks to Waldemar Knorr for tracking this down. llvm-svn: 57124
* Add instruction names as comments to InstBits entries.Evan Cheng2008-09-171-5/+3
| | | | llvm-svn: 56275
* Eliminate a compile time warning.Evan Cheng2008-09-071-1/+1
| | | | llvm-svn: 55878
* Change getBinaryCodeForInstr prototype. First operand MachineInstr& should ↵Evan Cheng2008-09-021-1/+2
| | | | | | be const. Make corresponding changes. llvm-svn: 55623
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-3/+9
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
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