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path: root/llvm/utils/TableGen/CodeEmitterGen.cpp
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* remove a bunch of unused private methodsNuno Lopes2014-03-231-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) llvm-svn: 204560
* [TableGen] Don't assert, produce an error, when an instruction has too few ↵Hal Finkel2014-03-221-1/+12
| | | | | | | | | | | operands When an instruction's operand list does not have a sufficient number of operands to match with all of the variables that contribute to its encoding, instead of asserting inside a call to getSubOperandNumber, produce an informative error. llvm-svn: 204542
* [TableGen] Optionally forbid overlap between named and positional operandsHal Finkel2014-03-131-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are currently two schemes for mapping instruction operands to instruction-format variables for generating the instruction encoders and decoders for the assembler and disassembler respectively: a) to map by name and b) to map by position. In the long run, we'd like to remove the position-based scheme and use only name-based mapping. Unfortunately, the name-based scheme currently cannot deal with complex operands (those with suboperands), and so we currently must use the position-based scheme for those. On the other hand, the position-based scheme cannot deal with (register) variables that are split into multiple ranges. An upcoming commit to the PowerPC backend (adding VSX support) will require this capability. While we could teach the position-based scheme to handle that, since we'd like to move away from the position-based mapping generally, it seems silly to teach it new tricks now. What makes more sense is to allow for partial transitioning: use the name-based mapping when possible, and only use the position-based scheme when necessary. Now the problem is that mixing the two sensibly was not possible: the position-based mapping would map based on position, but would not skip those variables that were mapped by name. Instead, the two sets of assignments would overlap. However, I cannot currently change the current behavior, because there are some backends that rely on it [I think mistakenly, but I'll send a message to llvmdev about that]. So I've added a new TableGen bit variable: noNamedPositionallyEncodedOperands, that can be used to cause the position-based mapping to skip variables mapped by name. llvm-svn: 203767
* Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()David Woodhouse2014-01-281-5/+10
| | | | llvm-svn: 200349
* Support little-endian encodings in the FixedLenDecoderEmitterHal Finkel2013-12-171-37/+1
| | | | | | | | | | | | | | | The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). llvm-svn: 197532
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-1/+1
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* Fix issue with invalid flat operand numberEvandro Menezes2012-11-091-3/+1
| | | | | | | Avoid iterating over list of operands beyond the number of operands in it. PS: this fixes issue with revision #167634. llvm-svn: 167635
* Fix issue with invalid flat operand numberEvandro Menezes2012-11-091-1/+6
| | | | | | Avoid iterating over list of operands beyond the number of operands in it. llvm-svn: 167634
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-4/+4
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Re-work bit/bits value resolving in tblgenMichael Liao2012-09-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch is inspired by the failure of the following code snippet which is used to convert enumerable values into encoding bits to improve the readability of td files. class S<int s> { bits<2> V = !if(!eq(s, 8), {0, 0}, !if(!eq(s, 16), {0, 1}, !if(!eq(s, 32), {1, 0}, !if(!eq(s, 64), {1, 1}, {?, ?})))); } Later, PR8330 is found to report not exactly the same bug relevant issue to bit/bits values. - Instead of resolving bit/bits values separately through resolveBitReference(), this patch adds getBit() for all Inits and resolves bit value by resolving plus getting the specified bit. This unifies the resolving of bit with other values and removes redundant logic for resolving bit only. In addition, BitsInit::resolveReferences() is optimized to take advantage of this origanization by resolving VarBitInit's variable reference first and then getting bits from it. - The type interference in '!if' operator is revised to support possible combinations of int and bits/bit in MHS and RHS. - As there may be illegal assignments from integer value to bit, says assign 2 to a bit, but we only check this during instantiation in some cases, e.g. bit V = !if(!eq(x, 17), 0, 2); Verbose diagnostic message is generated when invalid value is resolveed to help locating the error. - PR8330 is fixed as well. llvm-svn: 163360
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-2/+35
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask.NAKAMURA Takumi2012-03-091-1/+1
| | | | | | ~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF. llvm-svn: 152407
* Fix support for encodings up to 64-bits in length. TableGen was silently ↵Owen Anderson2012-03-061-6/+6
| | | | | | truncating them to 32-bits prior to this. llvm-svn: 152148
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-241-7/+7
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Unconstify InitsDavid Greene2011-07-291-13/+13
| | | | | | Remove const qualifiers from Init references, per Chris' request. llvm-svn: 136531
* [AVX] Create Inits Via Factory MethodDavid Greene2011-07-291-1/+1
| | | | | | | Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. llvm-svn: 136486
* [AVX] Constify InitsDavid Greene2011-07-291-13/+13
| | | | | | | Make references to Inits const everywhere. This is the final step before making them unique. llvm-svn: 136485
* [AVX] Remove Mutating Members from InitsDavid Greene2011-07-291-4/+8
| | | | | | | Get rid of all Init members that modify internal state. This is in preparation for making references to Inits const. llvm-svn: 136483
* Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher2011-07-111-22/+16
| | | | | | in multiple buildbots. llvm-svn: 134936
* Use get(0 Instead of Create()David Greene2011-07-111-1/+1
| | | | | | Respond to some feedback asking for a name change. llvm-svn: 134921
* [AVX] Make Inits FoldableDavid Greene2011-07-111-16/+22
| | | | | | | | | | | | | | | | | | Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. llvm-svn: 134907
* Don't require pseudo-instructions to carry encoding information.Jim Grosbach2011-07-061-3/+6
| | | | | | | | | | For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. llvm-svn: 134539
* Fix a bug in tblgen that caused incorrect encodings on instructions that ↵Owen Anderson2011-04-281-1/+5
| | | | | | | | | specified operands with "bit" instead of "bits<1>". Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> llvm-svn: 130410
* Tidy up a bit.Jim Grosbach2011-02-031-3/+3
| | | | llvm-svn: 124832
* Fix a comment typo.Bob Wilson2011-01-271-1/+1
| | | | llvm-svn: 124450
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-1/+1
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* Move <map> include out of .h and into .cpp.Bill Wendling2010-12-131-0/+1
| | | | llvm-svn: 121661
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-1/+1
| | | | llvm-svn: 121659
* pull the code to get the operand value out of the loop.Chris Lattner2010-11-151-48/+58
| | | | llvm-svn: 119130
* split the giant encoder loop into two new helper functions.Chris Lattner2010-11-151-112/+122
| | | | llvm-svn: 119129
* reduce nesting and minor cleanups, no functionality change.Chris Lattner2010-11-151-87/+88
| | | | llvm-svn: 119128
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-3/+3
| | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
* Add support for specifying a PostEncoderMethod, which can perform ↵Owen Anderson2010-11-111-0/+4
| | | | | | | | post-processing after the automated encoding of an instruction. Not yet used. llvm-svn: 118759
* Support generating an MC'ized CodeEmitter directly. Maintain a reference to theJim Grosbach2010-11-031-5/+18
| | | | | | | Fixups list for the instruction so the operand encoders can add to it as needed. llvm-svn: 118206
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-0/+6
| | | | | | assumptions about stack layout. Specifically, LR must be saved next to FP. llvm-svn: 118026
* Tidy up.Jim Grosbach2010-11-021-3/+0
| | | | llvm-svn: 117987
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-6/+7
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Allow targets to optionally specify custom binary encoder functions forJim Grosbach2010-10-121-5/+20
| | | | | | | | operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. llvm-svn: 116353
* The assert() should reference to machine instr operand number, too.Jim Grosbach2010-10-111-2/+2
| | | | llvm-svn: 116243
* Make sure to use the machine instruction operand number. It doesn't alwaysJim Grosbach2010-10-111-0/+2
| | | | | | map one-to-one with the CodeGenInstruction operand number. llvm-svn: 116238
* When figuring out which operands match which encoding fields in an instruction,Jim Grosbach2010-10-111-6/+17
| | | | | | | try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). llvm-svn: 116211
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116018
* trailing whitespaceJim Grosbach2010-10-071-17/+17
| | | | llvm-svn: 115923
* Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen2010-07-021-40/+5
| | | | | | | | | list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. llvm-svn: 107520
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-011-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 llvm-svn: 102815
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-1/+1
| | | | llvm-svn: 100709
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-3/+3
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* look up instructions by record, not by name.Chris Lattner2010-03-191-1/+1
| | | | llvm-svn: 98904
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-3/+3
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
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