summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/AsmMatcherEmitter.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Revert "[TableGen] AsmMatcher: fix OpIdx computation when ↵Vitaly Buka2017-08-041-19/+3
| | | | | | | | | | HasOptionalOperands is true" Breaks check-llvm under ubsan. This reverts commit r309949. llvm-svn: 310008
* [TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is trueNirav Dave2017-08-031-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider the following instruction: "inst.eq $dst, $src" where ".eq" is an optional flag operand. The $src and $dst operands are registers. If we parse the instruction "inst r0, r1", the flag is not present and it will be marked in the "OptionalOperandsMask" variable. After the matching is complete we call the "convertToMCInst" method. The current implementation works only if the optional operands are at the end of the array. The "Operands" array looks like [token:"inst", reg:r0, reg:r1]. The first operand that must be added to the MCInst is the destination, the r0 register. The "OpIdx" (in the Operands array) for this register is 2. However, since the flag is not present in the Operands, the actual index for r0 should be 1. The flag is not present since we rely on the default value. This patch removes the "NumDefaults" variable and replaces it with an array (DefaultsOffset). This array contains an index for each operand (excluding the mnemonic). At each index, the array contains the number of optional operands that should be subtracted. For the previous example, this array looks like this: [0, 1, 1]. When we need to access the r0 register, we compute its index as 2 - DefaultsOffset[1] = 1. Patch by Alexandru Guduleasa! Reviewers: SamWot, nhaustov, niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35998 llvm-svn: 309949
* [TableGen] Fix some mismatches in the use of Namespace fields versus Target ↵Craig Topper2017-07-071-2/+2
| | | | | | | | | | | | name in some of our emitters. Some of our emitters were using the name of the Target to reference things that were created by others emitters using Namespace. Apparently all targets have the same Target name as their instruction and register Namespace field? Someone on IRC had a target that didn't do this and was getting build errors. This patch is a necessary, but maybe not sufficient fix. llvm-svn: 307358
* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-0/+43
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-19/+18
| | | | | | instead of a std::string. llvm-svn: 304347
* [TableGen] Make Record::getValueAsString and getValueAsListOfStrings return ↵Craig Topper2017-05-311-2/+6
| | | | | | | | | | | | StringRefs instead of std::string Internally both these methods just return the result of getValue on either a StringInit or a CodeInit object. In both cases this returns a StringRef pointing to a string allocated in the BumpPtrAllocator so its not going anywhere. So we can just pass that StringRef along. This is a fairly naive patch that targets just the build failures caused by this change. There's additional work that can be done to avoid creating std::string at call sites that still think getValueAsString returns a std::string. I'll try to clean those up in future patches. Differential Revision: https://reviews.llvm.org/D33710 llvm-svn: 304325
* Added LLVM_DUMP_METHOD attributes for MatchableInfo::dump(). Defined it only ↵Galina Kistanova2017-05-171-1/+3
| | | | | | if dump is enabled. llvm-svn: 303229
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
* Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule ↵Daniel Sanders2017-04-211-1/+1
| | | | | | | | | predicates and support the equivalent in GIRule. It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I haven't worked out why. Reverting to make it green while I figure it out. llvm-svn: 300978
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300964
* Spelling mistakes in comments. NFCI.Simon Pilgrim2017-03-311-1/+1
| | | | llvm-svn: 299197
* [tablegen] Use categories on options that only matter to one emitter.Daniel Sanders2017-03-271-2/+5
| | | | | | | | | | | | | | | | Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
* Move mnemonicIsValid to Mips target.Craig Topper2017-02-081-24/+0
| | | | | | | | | | | | | | | | | | | | Summary: The Mips target is the only user of mnemonicIsValid. This patch moves this method from AsmMatcherEmitter.cpp to MipsAsmParser.cpp, getting rid of the method in all other targets where it generated warnings about an unused function. Patch by Gonsolo. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: sdardis Differential Revision: https://reviews.llvm.org/D28748 llvm-svn: 294400
* Summary: Currently there is no way to disable deprecated warning from asm ↵Weiming Zhao2016-12-051-1/+3
| | | | | | | | | | | | | | | | | | | | like this clang -target arm deprecated-asm.s -c deprecated-asm.s:30:9: warning: use of SP or PC in the list is deprecated stmia r4!, {r12-r14} We have to have an option what can disable it. Patched by Yin Ma! Reviewers: joey, echristo, weimingz Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27219 llvm-svn: 288734
* TableGen/AsmMatcherEmitter: Bring sorting check back under EXPENSIVE_CHECKSMatthias Braun2016-12-051-3/+13
| | | | | | | | | | | Bring the sorting check back that I removed in r288655 but put it under EXPENSIVE_CHECKS this time. Also document that this the check isn't purely about having a sorted list but also about operator < having the correct transitive behavior. Apply the same to the other check in the file. llvm-svn: 288693
* TableGen/AsmMatcherEmitter: Trust that stable_sort worksMatthias Braun2016-12-051-10/+0
| | | | | | | | | A debug build of AsmMatcherEmitter would use a quadratic algorithm to check whether std::stable_sort() actually sorted. Let's hope the authors of our C++ standard library did that testing for us. Removing the check gives a 3x speedup in the X86 case. llvm-svn: 288655
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-4/+4
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Check that emitted instructions meet their predicates on all targets except ↵Daniel Sanders2016-11-191-27/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM, Mips, and X86. Summary: * ARM is omitted from this patch because this check appears to expose bugs in this target. * Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2. * X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure. Patches for ARM and Mips will follow. Depends on D25617 Reviewers: tstellarAMD, jmolloy Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D25618 llvm-svn: 287439
* [tablegen] Merge duplicate definitions of getMinimalTypeForRange. NFC.Daniel Sanders2016-11-191-11/+1
| | | | | | | | | | | | Summary: Depends on D25614 Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25617 llvm-svn: 287438
* Fix -Wunused introduced in r286945 for release builds.Daniel Sanders2016-11-151-0/+2
| | | | llvm-svn: 286946
* [tablegen] Extract portions of AsmMatcherEmitter for re-use by another ↵Daniel Sanders2016-11-151-89/+11
| | | | | | | | | | | | | | | | | | | generator. NFC. Summary: This change is preparation for a change that will allow targets to verify that the instructions they emit meet the predicates they specify. This is useful to ensure that C++ legalization/lowering/instruction-selection doesn't incorrectly select code for a different subtarget than intended. Such cases are not caught by the integrated assembler when emitting instructions directly to an object file. Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits, modocache Differential Revision: https://reviews.llvm.org/D25614 llvm-svn: 286945
* [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.hAlex Bradbury2016-11-011-9/+2
| | | | | | | | | | | | | | | As it stands, the OperandMatchResultTy is only included in the generated header if there is custom operand parsing. However, almost all backends make use of MatchOperand_Success and friends from OperandMatchResultTy for e.g. parseRegister. This is a pain when starting an AsmParser for a new backend that doesn't yet have custom operand parsing. Move the enum to MCTargetAsmParser.h. This patch is a prerequisite for D23563 Differential Revision: https://reviews.llvm.org/D23496 llvm-svn: 285705
* Switch SmallSetVector to use DenseSet when it overflows its inline space.Justin Lebar2016-10-211-15/+17
| | | | | | | | | | | | | | | | | | | | Summary: SetVector already used DenseSet, but SmallSetVector used std::set. This leads to surprising performance differences. Moreover, it means that the set of key types accepted by SetVector and SmallSetVector are quite different! In order to make this change, we had to convert some callsites that used SmallSetVector<std::string, N> to use SmallSetVector<CachedHashString, N> instead. Reviewers: timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25648 llvm-svn: 284887
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-101-1/+1
| | | | llvm-svn: 283814
* MC: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
| | | | llvm-svn: 283691
* [TableGen] AsmMatcher: Add AsmVariantName to Instruction class.Sam Kolton2016-09-081-0/+11
| | | | | | | | | | | | | | Summary: This allows specifying instructions that are available only in specific assembler variant. If AsmVariantName is specified then instruction will be presented only in MatchTable for this variant. If not specified then assembler variants will be determined based on AsmString. Also this allows splitting assembler match tables in same way as it is done in dissasembler. Reviewers: ab, tstellarAMD, craig.topper, vpykhtin Subscribers: wdng Differential Revision: https://reviews.llvm.org/D24249 llvm-svn: 280952
* Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2016-08-121-11/+8
| | | | | | No functionality change is intended. llvm-svn: 278443
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-2/+1
| | | | | | | | | If the result of the find is only used to compare against end(), just use is_contained instead. No functionality change is intended. llvm-svn: 278433
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-271-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [TableGen] Use StringRef::compare instead of != and <. NFC.Ahmed Bougacha2016-06-231-2/+2
| | | | | | | | | The previous code would always do 1 or 2 prefix compares; explicitly only do one. This speeds up debug -gen-asm-matcher by ~10% (e.g. X86: 40s -> 35s). llvm-svn: 273583
* [TableGen] AsmMatcher: support for default values for optional operandsSam Kolton2016-05-061-31/+117
| | | | | | | | | | | | | | Summary: This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst. Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented. Reviewers: tstellarAMD, ab, craig.topper Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits Differential Revision: http://reviews.llvm.org/D18242 llvm-svn: 268726
* [NFC] Header cleanupMehdi Amini2016-04-181-2/+1
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [TableGen] AsmMatcherEmitter.cpp: replace a sequence of "if" to "switch" in ↵Valery Pykhtin2016-04-051-2/+6
| | | | | | | | emitValidateOperandClass. Differential Revision: http://reviews.llvm.org/D18394 llvm-svn: 265412
* [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if ↵Nikolay Haustov2016-03-011-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | it is not present Previosy, if actual instruction have one of optional operands then other optional operands listed before this also should be presented. For example instruction v_fract_f32 v0, v1, mul:2 have one optional operand - OMod and do not have optional operand clamp. Previously this was not allowed because clamp is listed before omod in AsmString: string AsmString = "v_fract_f32$vdst, $src0_modifiers$clamp$omod"; Making this work required some hacks (both OMod and Clamp match classes have same PredicateMethod). Now, if MatchInstructionImpl meets formal optional operand that is not presented in actual instruction it skips this formal operand and tries to match current actual operand with next formal. Patch by: Sam Kolton Review: http://reviews.llvm.org/D17568 [AMDGPU] Assembler: Check immediate types for several optional operands in predicate methods With this change you should place optional operands in order specified by asm string: clamp -> omod offset -> glc -> slc -> tfe Fixes for several tests. Depends on D17568 Patch by: Sam Kolton Review: http://reviews.llvm.org/D17644 llvm-svn: 262314
* TableGen: Add IsOptional field to AsmOperandClassTom Stellard2016-02-051-1/+15
| | | | | | | | | | | | | | | Summary: This makes it possible to specify some operands as optional to the AsmMatcher. Setting this field to true will prevent the AsmMatcher from emitting 'too few operands' errors when there are missing optional operands. Reviewers: olista01, ab Subscribers: nhaustov, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15755 llvm-svn: 259913
* [TableGen] Add 'register alternative name matching' supportDylan McKay2016-02-031-0/+34
| | | | | | | | | | | | | | | | | Summary: This adds a new attribute which targets can set in TableGen which causes a function to be generated which matches register alternative names. This is very similar to `ShouldEmitMatchRegisterName`, except it works on alt names. This patch is currently used by the out of tree part of the AVR backend. It reduces code duplication greatly, and has the effect that you do not need to hardcode altname to register mappings in C++. It will not work on targets which have registers which share the same aliases. Reviewers: stoklund, arsenm, dsanders, hfinkel, vkalintiris Subscribers: hfinkel, dylanmckay, llvm-commits Differential Revision: http://reviews.llvm.org/D16312 llvm-svn: 259636
* Fix Clang-tidy readability-redundant-control-flow warnings; other minor fixes.Eugene Zelenko2016-02-021-11/+5
| | | | | | Differential revision: http://reviews.llvm.org/D16793 llvm-svn: 259539
* [TableGen] Fix sort order of asm operand classesOliver Stannard2016-01-251-20/+85
| | | | | | | | | | | | | | | | | | | | | | This is a fix for https://llvm.org/bugs/show_bug.cgi?id=22796. The previous implementation of ClassInfo::operator< allowed cycles of classes such that x < y < z < x, meaning that a list of them cannot be correctly sorted, and the sort order could differ with different standard libraries. The original implementation sorted classes by ValueName if they were otherwise equal. This isn't strictly necessary, but some backends seem to accidentally rely on it. If I reverse this comparison I get 8 test failures spread across the AArch64, Mips and X86 backends, so I have left it in until those backends can be fixed. There was one case in the X86 backend where the observable behaviour of the assembler is changed by this patch. This was because some of the memory asm operands were not marked as children of X86MemAsmOperand. Differential Revision: http://reviews.llvm.org/D16141 llvm-svn: 258677
* [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need ↵Craig Topper2016-01-171-1/+1
| | | | | | to make an iterator_range when we already have a function that returns an ArrayRef. NFC llvm-svn: 258019
* [TableGen] Replace a logically negated xor of bools with just an equality ↵Craig Topper2016-01-031-1/+1
| | | | | | comparison for readability. NFC llvm-svn: 256699
* [TableGen] Use std::find_if and a lambda instead of manual loops.Craig Topper2016-01-031-9/+10
| | | | llvm-svn: 256698
* [TableGen] Fix a bug introduced in r256627. If the switch was not emitted we ↵Craig Topper2016-01-031-2/+3
| | | | | | still emitted a closing curly brace. llvm-svn: 256697
* [TableGen] Use range-based for loops. NFCCraig Topper2016-01-031-20/+13
| | | | llvm-svn: 256696
* [TableGen] Modify the AsmMatcherEmitter to only apply the table growth from ↵Craig Topper2015-12-311-63/+110
| | | | | | | | | | | | | | r252440 to the Hexagon target. This restores the previous behavior of not including the mnemonic in the classes table for every target that starts instruction lines with the mnemonic. Not only did the table size increase by 1 entry, but the class enum increased in size which caused every class in the array to increase in size. It also grew the size of the function that parsers tokens into classes by a substantial amount. This adds a new HasMnemonicFirst flag to all AsmParsers. It's set to 1 by default and Hexagon target overrides it to 0. For the X86 target alone this recovers 324KB of size on the llvm-mc executable. I believe the current state is still a bad design choice for the Hexagon target as it causes most of the parsing to do a linear search through the entire match table to comparing operands against every instruction until it finds one that works. At least for the other targets we do a binary search based on mnemonic over which to do the linear scan. llvm-svn: 256669
* [TableGen] Use range-based for loops. NFCCraig Topper2015-12-311-8/+3
| | | | llvm-svn: 256668
* [TableGen] Move determination of IsIsolatedToken into the tokenizer instead ↵Craig Topper2015-12-311-31/+33
| | | | | | of trying to search characters around the token. No functional change intended. Verified for in-tree targets. llvm-svn: 256660
* [TableGen] Remove unnecessary conversion from StringRef to std::string when ↵Craig Topper2015-12-301-2/+2
| | | | | | outputting to a raw_ostream. NFC llvm-svn: 256628
* [TableGen] Remove raw_string_ostream by just emitting the header for the ↵Craig Topper2015-12-301-20/+20
| | | | | | switch the first time we emit a case. If the header was never emitted just print the default at the end. NFC llvm-svn: 256627
* [TableGen] Use range-based for loops. NFCCraig Topper2015-12-301-4/+4
| | | | llvm-svn: 256626
* [TableGen] Move more things that come from variant into the AsmVariantInfo ↵Craig Topper2015-12-301-12/+12
| | | | | | class so we can reduce some parameters. NFC llvm-svn: 256625
OpenPOWER on IntegriCloud