| Commit message (Collapse) | Author | Age | Files | Lines |
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failed because a subtarget feature was not enabled. Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode. Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.
This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).
llvm-svn: 113166
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llvm-svn: 113165
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into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
llvm-svn: 113163
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out of AsmMatcherEmitter.cpp into its own class.
llvm-svn: 113137
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target specific parsers can adapt the TargetAsmParser to this.
llvm-svn: 110888
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llvm-svn: 110789
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warning, for now.
llvm-svn: 110779
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attributes as part of the matcher.
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.
llvm-svn: 108677
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llvm-svn: 108130
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reliably.
llvm-svn: 104806
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instead of just one.
llvm-svn: 104452
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name (for example, to allow targets to interpose the actual MatchInstruction
function).
llvm-svn: 102987
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to a vector that CGT stores instead of synthesizing it on every
call.
llvm-svn: 98910
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llvm-svn: 98906
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to allow custom post-processing of matched instructions.
llvm-svn: 98857
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matcher is now free of implicit operands!
- Still need to clean up the code now that we don't to worry about implicit
operands, and to make it a hard error if an instruction fails to specify all
of its operands for some reason.
llvm-svn: 95956
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llvm-svn: 95802
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- Pretty messy, but we need to rework how we handle tied operands in MCInst
anyway.
llvm-svn: 95774
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llvm-svn: 95627
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is still deterministic even amongst ambiguous instructions (eventually ambiguous
match orders will be a hard error, but we aren't there yet).
llvm-svn: 95157
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in the order they were declared.
llvm-svn: 94868
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be static. Also made it possible for clients to get it
and no other functions from ...GenAsmMatcher.inc by
defining REGISTERS_ONLY before including GenAsmMatcher.inc.
This sets the stage for target-specific lexers that can
identify registers and return AsmToken::Register as
appropriate.
llvm-svn: 94266
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llvm-svn: 94261
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the new ParseInstruction method just parses and returns a list of
target operands. A new MatchInstruction interface is used to
turn the operand list into an MCInst.
This requires new/deleting all the operands, but it also gives
targets the ability to use polymorphic operands if they want to.
llvm-svn: 93469
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We now match all of 403.gcc (as emitted by clang). :)
llvm-svn: 78750
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- Used to mark fake instructions which don't correspond to an actual machine
instruction (or are duplicates of a real instruction). This is to be used for
"special cases" in the .td files, which should be ignored by things like the
assembler and disassembler. We still need a good solution to handle pervasive
duplication, like with the Int_ instructions.
- Set the bit on fake "mov 0" style instructions, which allows turning an
assembler matcher warning into a hard error.
- -2 FIXMEs.
llvm-svn: 78731
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used to strip hard coded comments out of .td assembly strings.
llvm-svn: 78716
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related.
llvm-svn: 78706
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- This drops us to 123 ambiguous instructions (previously ~500) on X86.
llvm-svn: 78636
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on target specific operands for testing class membership and converting to
MCInst operands.
llvm-svn: 78597
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explicit parser match classes.
llvm-svn: 78588
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structure.
llvm-svn: 78581
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instruction operands.
llvm-svn: 78565
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llvm-svn: 78533
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make it easier to see interesting ambiguities.
- Also, check that user doesn't try to redefine the super class. This is a wart
in the current design, in that assembler match classes aren't explicitly
declared somewhere (so there isn't a unique place to declare the super
class). This should probably be fixed.
llvm-svn: 78532
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- We can now discriminate SUB32ri8 from SUB32ri, for example.
llvm-svn: 78530
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- We want the ordering operation to be simple, since we run it on every
match. The old ordering is also not a strict weak ordering when there are
ambiguities, which makes MSVC unhappy.
- While we are at it, detect all ambiguities instead of just the adjacent
ones. There are actually 655, for X86.
llvm-svn: 78526
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-2 FIXMEs.
llvm-svn: 78523
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ambiguities.
- Currently there are 483 ambiguities to resolve. :)
llvm-svn: 78522
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llvm-svn: 78520
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llvm-svn: 78518
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- Track whether we need to insert an explicit 'break'.
- Invert conditional when matching a single prefix to reduce
nesting/bracing/breaking.
- wc -l of X86GenAsmMatcher.inc decreased by 10%. :)
llvm-svn: 78513
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Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.
llvm-svn: 78504
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much more efficient way than a sequence of if's. Switch MatchRegisterName
to use it. It would be nice if someone could factor this out to a shared
place in tblgen :)
llvm-svn: 78492
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llvm-svn: 78487
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llvm-svn: 78486
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llvm-svn: 78462
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- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
llvm-svn: 78461
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so that terminal states are as simple as possible.
- If we were willing to assume that the order that operands get inserted in the
MCInst is fixed we could actually dispose with this altogether, although it
might be nice to have the flexibility to change it later.
llvm-svn: 78458
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routine.
llvm-svn: 78408
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