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path: root/llvm/utils/TableGen/AsmMatcherEmitter.cpp
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* a bunch of random cleanup, move a helper to CGT where it belongs.Chris Lattner2010-11-021-50/+35
| | | | llvm-svn: 118031
* add and update comments.Chris Lattner2010-11-021-2/+9
| | | | llvm-svn: 118025
* refactor/cleanup MatchableInfo by eliminating the Tokens array,Chris Lattner2010-11-021-126/+127
| | | | | | | | merging it into a Token field in Operand, and moving the first token to an explicit mnemonic field. These were parallel arrays before (except for the mnemonic) which kept confusing me. llvm-svn: 118024
* rename operands -> asmoperands to be more descriptive.Chris Lattner2010-11-021-28/+30
| | | | llvm-svn: 117993
* fix computation of ambiguous instructions to not ignore the mnemonic.Chris Lattner2010-11-011-3/+7
| | | | | | FWIW, X86 has 254 ambiguous instructions. llvm-svn: 117979
* give MatchableInfo::Operand a constructorChris Lattner2010-11-011-11/+7
| | | | llvm-svn: 117968
* Implement enough of the missing instalias support to getChris Lattner2010-11-011-4/+8
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
* rename InstructionInfo -> MatchableInfo since it nowChris Lattner2010-11-011-65/+74
| | | | | | | | represents InstAliases as well. Rename isAssemblerInstruction -> Validate since that is what it does (modulo the ARM $lane hack). llvm-svn: 117899
* refactor initialization of InstructionInfo to be sharable betweenChris Lattner2010-11-011-27/+46
| | | | | | | instructions and InstAliases. Start creating InstructionInfo's for Aliases. llvm-svn: 117898
* make the asm matcher emitter reject instructions that have commentsChris Lattner2010-11-011-33/+24
| | | | | | | in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. llvm-svn: 117897
* refactor InstructionInfo to not have a pointer to CodeGenInstructionChris Lattner2010-11-011-88/+89
| | | | | | | member, and make isAssemblerInstruction() a method (pushing some code around inside it). llvm-svn: 117895
* define a new CodeGenInstAlias. It has an asmstring and operand list for now,Chris Lattner2010-11-011-0/+9
| | | | | | todo: the result field. llvm-svn: 117894
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-15/+16
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* avoid needless throw/catch/rethrow, stringref'ize some simple stuff.Chris Lattner2010-11-011-5/+2
| | | | llvm-svn: 117892
* eliminate the old InstFormatName which is always "AsmString",Chris Lattner2010-11-011-1/+1
| | | | | | simplify CodeGenInstruction. No functionality change. llvm-svn: 117891
* all predicates on an MnemonicAlias must be AssemblerPredicates.Chris Lattner2010-11-011-6/+10
| | | | llvm-svn: 117890
* change the singleton register handling code to be based on Record*'sChris Lattner2010-11-011-48/+41
| | | | | | instead of strings, simplifying it. llvm-svn: 117889
* Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch ofChris Lattner2010-11-011-83/+92
| | | | | | | | | argument passing. Consolidate all SingletonRegister detection and handling into a new InstructionInfo::getSingletonRegisterForToken method instead of having it scattered about. No change in generated .inc files. llvm-svn: 117888
* move FlattenVariants out of AsmMatcherEmitter into a sharedChris Lattner2010-11-011-51/+4
| | | | | | | | CodeGenInstruction::FlattenAsmStringVariants method. Use it to simplify the code in AsmWriterInst, which now no longer needs to worry about variants. llvm-svn: 117886
* add a FIXME, $lane in ARM is an issue that needs to be resolved beforeChris Lattner2010-11-011-1/+2
| | | | | | this can start rejecting instructions. llvm-svn: 117885
* reject instructions that contain a \n in their asmstring. MarkChris Lattner2010-11-011-7/+10
| | | | | | | various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. llvm-svn: 117884
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-311-15/+0
| | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. llvm-svn: 117862
* two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner2010-10-311-8/+16
| | | | | | | and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. llvm-svn: 117861
* reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner2010-10-311-28/+23
| | | | | | got a dulicated line). llvm-svn: 117860
* revert r117858 while I check out a failure I missed.Chris Lattner2010-10-311-26/+29
| | | | llvm-svn: 117859
* the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner2010-10-311-29/+26
| | | | | | | | | | | Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. llvm-svn: 117858
* have GetAliasRequiredFeatures get its features fromChris Lattner2010-10-301-30/+22
| | | | | | | AsmMatcherInfo so we don't have two places that know the feature -> enum mapping. No functionality change. llvm-svn: 117845
* simplify code that creates SubtargetFeatureInfo, ensuring that features Chris Lattner2010-10-301-19/+33
| | | | | | that are only used by MnemonicAliases will be found. llvm-svn: 117844
* fix typos and some serious bugs in feature handling (but not forChris Lattner2010-10-301-3/+7
| | | | | | | cases that are currently exercised). Thanks to Frits van Bommel for the great review! llvm-svn: 117840
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-28/+12
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-301-13/+65
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* fix build problemChris Lattner2010-10-301-3/+3
| | | | llvm-svn: 117828
* diagnose targets that define two alises with the same 'from' mnemonicChris Lattner2010-10-301-5/+30
| | | | | | | with a useful error message instead of having tblgen explode with an assert. llvm-svn: 117827
* emit the mnemonic aliases in their own helper function instead ofChris Lattner2010-10-301-6/+17
| | | | | | inline into MatchInstructionImpl. llvm-svn: 117826
* implement (and document!) the first kind of MC assembler alias, which Chris Lattner2010-10-301-4/+26
| | | | | | | just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. llvm-svn: 117815
* trailing whitespaceJim Grosbach2010-10-291-85/+85
| | | | llvm-svn: 117724
* fix the asmmatcher generator to handle targets with no RegisterPrefixChris Lattner2010-10-281-22/+34
| | | | | | | (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. llvm-svn: 117606
* A few 80 column cleanupsJim Grosbach2010-10-081-1/+2
| | | | llvm-svn: 116069
* attempt to appease msvcChris Lattner2010-09-071-0/+3
| | | | llvm-svn: 113198
* fix comment typosGabor Greif2010-09-071-2/+2
| | | | llvm-svn: 113197
* generalize my previous operand loc info hack. If the same operandChris Lattner2010-09-061-7/+9
| | | | | | | | | | | | | is busted for all variants, report it as the location. This allows us to get the operand right for bugs like: t.s:3:12: error: invalid operand for instruction outb %al, %gs ^ Even though there are reg/imm and reg/reg forms of this instruction. llvm-svn: 113183
* in the case where an instruction only has one implementationChris Lattner2010-09-061-10/+27
| | | | | | | | | | | | | | | | | | | | of a mneumonic, report operand errors with better location info. For example, we now report: t.s:6:14: error: invalid operand for instruction cwtl $1 ^ but we fail for common cases like: t.s:11:4: error: invalid operand for instruction addl $1, $1 ^ because we don't know if this is supposed to be the reg/imm or imm/reg form. llvm-svn: 113178
* Now that we know if we had a total fail on the instruction mnemonic, Chris Lattner2010-09-061-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | give a more detailed error. Before: t.s:11:4: error: unrecognized instruction addl $1, $1 ^ t.s:12:4: error: unrecognized instruction f2efqefa $1 ^ After: t.s:11:4: error: invalid operand for instruction addl $1, $1 ^ t.s:12:4: error: invalid instruction mnemonic 'f2efqefa' f2efqefa $1 ^ This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands" llvm-svn: 113176
* simplify DEBUG_WITH_TYPE usageChris Lattner2010-09-061-13/+10
| | | | llvm-svn: 113174
* this if can now be an assert.Chris Lattner2010-09-061-2/+2
| | | | llvm-svn: 113173
* ;Chris Lattner2010-09-061-1/+1
| | | | llvm-svn: 113172
* now that the opcode is trivially exposed, start matching instructionsChris Lattner2010-09-061-6/+22
| | | | | | | by doing a binary search over the mnemonic instead of doing a linear search through all possible instructions. This implements rdar://7785064 llvm-svn: 113171
* emit the match table at global scope instead of within the Chris Lattner2010-09-061-20/+25
| | | | | | | MatchInstructionImpl. This makes it easier to read/understand MatchInstructionImpl. llvm-svn: 113170
* special case the mnemonic operand of the instruction in the Chris Lattner2010-09-061-8/+29
| | | | | | | | | | | generated matcher, emiting it as a column in the MatchEntry table instead of forcing it to go through classification and everything else. Making it be classified caused tblgen to produce a ton of one-off classes for each mneumonic. This should reduce the size of the generated matcher significantly while paving the way for future improvements. llvm-svn: 113169
* The "ambiguous instructions" check only produces anything with -debug,Chris Lattner2010-09-061-21/+22
| | | | | | so only do the N^2 loop with debug mode. llvm-svn: 113168
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