| Commit message (Collapse) | Author | Age | Files | Lines |
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Also, some minor cleanup.
llvm-svn: 165647
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Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.
There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.
llvm-svn: 165646
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llvm-svn: 165324
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MSVC compiler.
llvm-svn: 165174
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llvm-svn: 164983
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map constraints and MCInst operands to inline asm operands. This replaces the
getMCInstOperandNum() function.
The logic to determine the constraints are not in place, so we still default to
a register constraint (i.e., "r"). Also, we no longer build the MCInst but
rather return just the opcode to get the MCInstrDesc.
llvm-svn: 164979
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Also remove an unused argument.
llvm-svn: 164567
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llvm-svn: 164548
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llvm-svn: 164420
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llvm-svn: 164406
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Fixes an observed instance of nondeterministic TableGen output.
Review by Jakob.
llvm-svn: 164191
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Fixes an observed instance of nondeterministic TableGen output.
Review by Jakob.
llvm-svn: 164190
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the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets.
llvm-svn: 164109
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on in tree targets. Saving static data space.
llvm-svn: 164108
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llvm-svn: 164088
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llvm-svn: 164086
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parameters.
llvm-svn: 163984
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llvm-svn: 163726
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llvm-svn: 163187
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llvm-svn: 163186
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llvm-svn: 163125
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the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.
llvm-svn: 163124
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MCTargetAsmParser class.
llvm-svn: 163122
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llvm-svn: 163119
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llvm-svn: 163118
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llvm-svn: 163104
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MatchInstructionImpl() function.
These values are used by the ConvertToMCInst() function to index into the
ConversionTable. The values are also needed to call the GetMCInstOperandNum()
function.
llvm-svn: 163101
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function nowadays.
llvm-svn: 163030
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the ConvertToMCInst() return void, rather then a bool. Update all the cvt
functions as well.
llvm-svn: 162961
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llvm-svn: 162946
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llvm-svn: 162945
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an 80-column violation in the generated code. No functional change intended.
llvm-svn: 162944
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AsmMatcherEmitter. This function maps inline assembly operands to MCInst
operands.
For example, '__asm mov j, eax' is represented by the follow MCInst:
<MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0>
<MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>>
The first 5 MCInst operands are a result of j matching as a memory operand
consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0),
Expr (Expr:(j), and a MemSegReg (Reg:0). The 6th MCInst operand represents
the eax register (Reg:43).
This translation is necessary to determine the Input and Output Exprs. If a
single asm operand maps to multiple MCInst operands, the index of the first
MCInst operand is returned. Ideally, it would return the operand we really
care out (i.e., the Expr:(j) in this case), but I haven't found an easy way
of doing this yet.
llvm-svn: 162920
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Adding arbitrary records to ARM.td would break
basic-arm-instructions.s because selection of nop vs mov r0,r0 was
ambiguous (this will be tested by a subsequent addition to ARM.td).
An imperfect but sensible fix is to give precedence to match rules
that have more constraints.
llvm-svn: 162824
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When reporting an error for a defm, we would previously only report the
location of the outer defm, which is not always where the error is.
Now we also print the location of the expanded multiclass defs:
lib/Target/X86/X86InstrSSE.td:2902:12: error: foo
defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
^
lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
^
lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass
def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
^
llvm-svn: 162409
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No change in interface or functionality. Purely under-the-hood
details of the generated function that change.
The X86 assembly parser is reduced in size by over 15% and ARM by
over 10%.
No performance change by my measurements.
llvm-svn: 162337
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llvm-svn: 162292
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Patch by Vladimir Medic.
llvm-svn: 162124
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llvm-svn: 161298
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user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class.
llvm-svn: 160327
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Make sure the tblgen'erated asm matcher correctly returns numoperands+1
as the ErrorInfo when the problem was that there weren't enough operands
specified.
rdar://9142751
llvm-svn: 160144
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Don't override a custom diagnostic w/ a generic InvalidOperand, all else
being equal.
llvm-svn: 159238
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"Invalid operand" may be a completely correct diagnostic, but it's often
insufficiently specific to really help identify and fix the problem in
assembly source. Allow a target to specify a more-specific diagnostic kind
for each AsmOperandClass derived definition and use that to provide
more detailed diagnostics when an operant of that class resulted in a
match failure.
rdar://8987109
llvm-svn: 159050
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When returning a 'cannot match due to missing CPU features' error code,
if there are multiple potential matches with different feature sets,
return the smallest set of missing features from the alternatives as
that's most likely to be the one that's desired.
llvm-svn: 158673
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The TableGenBackend base class doesn't do much, and will be removed
completely soon.
Patch by Sean Silva!
llvm-svn: 158311
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Previously, if an instruction definition was missing the mnemonic,
the next line would just assert(). Issue a real diagnostic instead.
llvm-svn: 156263
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be used by clang-tblgen.
llvm-svn: 156000
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only targets that want the function get it. This prevents other targets from getting an unused function warning.
llvm-svn: 155538
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When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
llvm-svn: 155499
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Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
add {Rd}, Rn, Rm // Rd is optional and is the same as Rn if omitted.
The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.
rdar://11255754
llvm-svn: 155172
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