summaryrefslogtreecommitdiffstats
path: root/llvm/unittests/Support/TargetParserTest.cpp
Commit message (Collapse)AuthorAgeFilesLines
* AArch64: add missing Apple CPU names and use them by default.Tim Northover2020-01-081-1/+46
| | | | | | | | Apple's CPUs are called A7-A13 in official communication, occasionally with weird suffixes which we probably don't need to care about. This adds each one and describes its features. It also switches the default CPU to the canonical name for Cyclone, but leaves legacy support in so that existing bitcode still compiles.
* TargetParserTest - testARMArch - stop bitwise operators on boolean warnings. ↵Simon Pilgrim2019-11-021-4/+5
| | | | | | NFCI. Ensure the test still runs all target checks but stop the static analyzer warnings.
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-24/+2
|
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Re-commit r366322 after some fixes TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Differential Revision: https://reviews.llvm.org/D64416 Patch by Javed Absar and Momchil Velikov llvm-svn: 367428
* [AArch64][SVE2] Rename bitperm feature to sve2-bitpermCullen Rhodes2019-07-261-3/+4
| | | | | | | | | | | | | | | | Summary: The bitperm feature flag is now prefixed with SVE2, as it is for all other SVE2 extensions Patch by Maciej Gabka. Reviewers: sdesmalen, rovka, chill, SjoerdMeijer, rengolin Reviewed By: SjoerdMeijer, rengolin Differential Revision: https://reviews.llvm.org/D65327 llvm-svn: 367124
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-251-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1. Neoverse E1 and Cortex-A65(&AE) only implement the AArch64 state of the Arm architecture. Neoverse N1 implements both AArch32 and AArch64. Cortex-A65: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65 Cortex-A65AE: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae Neoverse E1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1 Neoverse N1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 Patch by Diogo Sampaio and Pablo Barrio Reviewers: samparker, LukeCheeseman, sbaranga, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64406 llvm-svn: 367007
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-1/+0
| | | | | | This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) llvm-svn: 366355
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Patch by Javed Absar and Momchil Velikov Differential Revision: https://reviews.llvm.org/D64416 llvm-svn: 366322
* [clang][Driver][ARM] Favor -mfpu over default CPU featuresAlexandros Lamprineas2019-07-141-7/+8
| | | | | | | | | | | | | | | | When processing the command line options march, mcpu and mfpu, we store the implied target features on a vector. The change D62998 introduced a temporary vector, where the processed features get accumulated. When calling DecodeARMFeaturesFromCPU, which sets the default features for the specified CPU, we certainly don't want to override the features that have been explicitly specified on the command line. Therefore, the default features should appear first in the final vector. This problem became evident once I added the missing (unhandled) target features in ARM::getExtensionFeatures. Differential Revision: https://reviews.llvm.org/D63936 llvm-svn: 366027
* Follow up of rL363913. NFC.Sjoerd Meijer2019-06-241-5/+7
| | | | | | | Minor reshuffle in AArch64 targetparser unittest, solving a potential problem with querying iterators too early. llvm-svn: 364168
* TargetParserTest.ARMExtensionFeatures run out of memory on 32-bit (PR42316)Sjoerd Meijer2019-06-201-21/+68
| | | | | | | | | | | | | | | Nothing of these tests made much sense. Loops were iterating too much, and I also don't think it was actually testing anything. I think we simply want to check that AEK_SOME_EXT returns "+some_ext". I've given the AArch64 tests the same treatment as they very similarly didn't made any sense either. This fixes PR42316. Differential Revision: https://reviews.llvm.org/D63569 llvm-svn: 363913
* [test] Fix TargetParserTest runtime.Jordan Rupprecht2019-06-191-2/+5
| | | | | | | | r363780 fixes extreme memory growth by using a new std::vector every loop iteration, but causes runtime to go up (and occasionally timeout in certain situations) because of constructor cost every loop iteration. Fix this by moving the constructor back out, but clearing contents in the loop. Also apply this to the AArch64 features test case, which seems to use the same pattern. llvm-svn: 363851
* Make TargetParserTest.ARMExtensionFeatures not run out of memory on 32-bit ↵Hans Wennborg2019-06-191-2/+3
| | | | | | | | | (PR42316) The test still probably shouldn't run this loop 17 million times, but at least now it won't run out of memory. llvm-svn: 363780
* [ARM] add target arch definitions for 8.1-M and MVESjoerd Meijer2019-05-301-4/+11
| | | | | | | | | | | | | | | | | This adds: - LLVM subtarget features to make all the new instructions conditional on, - CPU and FPU names for use on clang's command line, with default FPUs set so that "armv8.1-m.main+fp" and "armv8.1-m.main+fp.dp" will select the right FPU features, - architecture extension names "mve" and "mve.fp", - ABI build attribute support for v8.1-M (a new value for Tag_CPU_arch) and MVE (a new actual tag). Patch mostly by Simon Tatham. Differential Revision: https://reviews.llvm.org/D60698 llvm-svn: 362090
* arm64_32: add some unittests that were in the wrong commit.Tim Northover2019-05-151-0/+3
| | | | | | | Accidentally dropped them when committing the arm64_32 binutils support. There's no change to real code. llvm-svn: 360763
* [AArch64][SVE2] Add SVE2 target features to backend and TargetParserCullen Rhodes2019-05-131-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds the following features defined by Arm SVE2 architecture extension: sve2, sve2-aes, sve2-sm4, sve2-sha3, bitperm For existing CPUs these features are declared as unsupported to prevent scheduler errors. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewers: SjoerdMeijer, sdesmalen, ostannard, rovka Reviewed By: SjoerdMeijer, rovka Subscribers: rovka, javed.absar, tschuett, kristof.beyls, kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61513 llvm-svn: 360573
* [AArch64, ARM] Add support for Exynos M5Evandro Menezes2019-03-221-2/+24
| | | | | | Add Exynos M5 support and test cases. llvm-svn: 356793
* [AArch64] Update for ExynosEvandro Menezes2019-03-211-5/+5
| | | | | | Fix the feature set for Exynos M4 by removing support for `+fp16fml` and fix test case. llvm-svn: 356698
* [ARM] Add Cortex-M35PLuke Cheeseman2019-02-261-1/+3
| | | | | | | | | | - Add LLVM backend support for Cortex-M35P - Documentation can be found at https://developer.arm.com/products/processors/cortex-m/cortex-m35p Differentail Revision: https://reviews.llvm.org/D57763 llvm-svn: 354868
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-2/+26
| | | | | | | | - Add LLVM backend support for Cortex-A76 and Cortex-A76AE - Documentation can be found at https://developer.arm.com/products/processors/cortex-a/cortex-a76 llvm-svn: 354788
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [AArch64] Create feature set for Exynos M4Evandro Menezes2019-01-111-7/+18
| | | | | | Complete the feature set for Exynos M4 and update test cases. llvm-svn: 350953
* [AArch64] Add command-line option predresDiogo N. Sampaio2019-01-041-1/+3
| | | | | | | | | | | Prediction control instructions are only mandatory from v8.5a onwards but is optional from Armv8.0-A. This patch adds a command line option to enable it by it's own. Differential Revision: https://reviews.llvm.org/D56007 llvm-svn: 350385
* [ARM] Add command-line option for SBDiogo N. Sampaio2019-01-031-1/+2
| | | | | | | | | | | | | | | SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also renames FeatureSpecRestrict to FeatureSB. Reviewed By: olista01, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55990 llvm-svn: 350299
* [AArch64] Add command-line option for SBDiogo N. Sampaio2018-12-281-1/+2
| | | | | | | | | | | | | | | SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also moves to FeatureSB the old FeatureSpecRestrict. Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55921 llvm-svn: 350126
* [NFC][AArch64] Remove duplicate Arch list in target parser testsDavid Spickett2018-12-101-6/+1
| | | | | | | | | | The list generated in the target parser tests is the same as the one in the AArch64 target parser. Use that one instead. Differential Revision: https://reviews.llvm.org/D55509 llvm-svn: 348757
* [AArch64] Add command-line option for SSBSPablo Barrio2018-12-031-2/+3
| | | | | | | | | | | | | | | | | | | | | Summary: SSBS (Speculative Store Bypass Safe) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SSBS, as it was previously only possible to enable by selecting -march=armv8.5-a. Similar patch upstream in GNU binutils: https://sourceware.org/ml/binutils/2018-09/msg00274.html Reviewers: olista01, samparker, aemerson Reviewed By: samparker Subscribers: javed.absar, kristof.beyls, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D54629 llvm-svn: 348137
* [ARM, AArch64] Move ARM/AArch64 target parsers intoDavid Spickett2018-11-281-2/+0
| | | | | | | | | | | | | | | | | separate files to enable future changes. This moves ARM and AArch64 target parsing into their own files. They are still accessible through TargetParser.h as before. Several functions in AArch64 which were just forwarders to ARM have been removed. All except AArch64::getFPUName were unused, and that was only used in a test. Which itself was overlapping one in ARM, so it has also been removed. Differential revision: https://reviews.llvm.org/D53980 llvm-svn: 347741
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-3/+30
| | | | | | | | | | | | Reviewers: t.p.northover, SjoerdMeijer, kristof.beyls Reviewed By: kristof.beyls Subscribers: olista01, javed.absar, kristof.beyls, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D53908 llvm-svn: 346546
* [AArch64][v8.5A] Add MTE as an optional AArch64 extensionOliver Stannard2018-10-021-1/+2
| | | | | | | | | | | | This adds the memory tagging extension, which is an optional extension introduced in v8.5A. The new instructions and registers will be added by subsequent patches. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52486 llvm-svn: 343563
* [ARM] Remove non-existent cpu arm1176j-s and use mpcore for v6kPeter Smith2018-09-281-4/+2
| | | | | | | | | | | | | | | The ARMTargetParser.def contains an entry for arm1176j-s which is the default for the ArmV6K architecture. This cpu does not exist, there are only arm1176jz-s and arm1176jzf-s and they are both architecture ArmV6KZ. The only CPUs that are actually ArmV6K are the mpcore, mpcore_nofpu and later revisions of the arm1136 family r1px (which we don't have a table entry for). This patch removes the arm1176j-s and makes mpcore the default for armv6k. Differential Revision: https://reviews.llvm.org/D52594 llvm-svn: 343303
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-271-1/+2
| | | | | | | | | | | | | This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
* [ARM/AArch64] Add target parser unit tests for Armv8.4-AOliver Stannard2018-09-261-5/+11
| | | | | | | | | | These were missed when adding Armv8.4-A support. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52471 llvm-svn: 343106
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-13/+22
| | | | | | | | | | | | | This patch allows targeting Armv8.5-A, adding the architecture to tablegen and setting the options to be identical to Armv8.4-A for the time being. Subsequent patches will add support for the different features included in the Armv8.5-A Reference Manual. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52470 llvm-svn: 343102
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-171-2/+23
| | | | | | | | | | | | | | | | | | Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
* [ARM/AArch64] TargetParserTest fixesBernard Ogden2018-08-171-2/+21
| | | | | | | | | Adds some missing tests for the FP16 extension, fixes an existing test that misnames it. Differential Revision: https://reviews.llvm.org/D50227 llvm-svn: 340012
* [AArch64, ARM] Add support for Samsung Exynos M4Evandro Menezes2018-06-061-8/+19
| | | | | | Create a separate feature set for Exynos M4 and add test cases. llvm-svn: 334115
* Fix signed/unsigned compare warning I introducedErich Keane2018-02-081-2/+2
| | | | | | | | 'size' of a vector is unsigned, and I accidentially compared it to an int through GTEST. I switched it to unsigned, which is the template parameter type anyway. llvm-svn: 324625
* [ARM] Add 'fillValidCPUArchList' to ARM targetsErich Keane2018-02-081-0/+28
| | | | | | | | | This is a support change for a CFE change (https://reviews.llvm.org/D42978) that allows march and -target-cpu to list the valid targets in a note. The changes are limited to the ARM/AArch64, since this is the only target that gets the CPU list from LLVM. llvm-svn: 324623
* [TargetParser] Add missing armv8l ARMv8 variant.Florian Hahn2018-01-091-17/+18
| | | | | | | | | | | | | | | | | | This change adds the missing armv8l variant as an alias of armv8 architecture. The issue was observed with several regressions in validation on armv8l hardware (for instance ExecutionEngine/frem.ll failed due to lack of neon fpu). Tested with regression testsuite passed without regression on ARM and x86_64. Patch by Yvan Roux. Reviewers: rengolin, rogfer01, olista01, fhahn Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D41859 llvm-svn: 322098
* [TargetParser] Check size before accessing architecture version.Florian Hahn2017-12-201-0/+6
| | | | | | | | | | | | | | | | | | Summary: This fixes a crash when invalid -march options like `armv` are provided. Based on a patch by Will Lovett. Reviewers: rengolin, samparker, mcrosier Reviewed By: samparker Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41429 llvm-svn: 321166
* [Unit][AArch64] Additional tests for target parsingEvandro Menezes2017-12-141-0/+4
| | | | | | Add Exynos M2/M3 to extension check. llvm-svn: 320762
* [AArch64] Add basic support for Qualcomm's Saphira CPU.Chad Rosier2017-09-251-0/+14
| | | | llvm-svn: 314105
* [TargetParser][AArch64] Add support for RDM feature in the target parser.Chad Rosier2017-08-241-7/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D37081 llvm-svn: 311659
* [ARM][AArch64] Add Armv8.3-a unittestsSam Parker2017-08-221-4/+10
| | | | | | | | Add Armv8.3-A to the architecture to the TargetParser unittests. Differential Revision: https://reviews.llvm.org/D36748 llvm-svn: 311450
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-2/+34
| | | | | | | | | | | | | | | | | | This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
* [TargetParser] Use enum classes for various ARM kind enums.Florian Hahn2017-07-271-143/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Using c++11 enum classes ensures that only valid enum values are used for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the need for checks that the provided values map to a proper enum value, allows us to get rid of AK_LAST and prevents comparing values from different enums. It also removes a bunch of static_cast from unsigned to enum values and vice versa, at the cost of introducing static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind. FPUKind and ArchExtKind are the only remaining old-style enum in TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style enum, but FPUKind can be converted too, but this patch is quite big, so could do this in a follow-up patch. I could also split this patch up a bit, if people would prefer that. Reviewers: rengolin, javed.absar, chandlerc, rovka Reviewed By: rovka Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35882 llvm-svn: 309287
* [AArch64] Add an SVE target feature to the backend and TargetParser.Amara Emerson2017-07-131-2/+3
| | | | | | | The feature will be used properly once assembler/disassembler support begins to land. llvm-svn: 307917
* Re-sort #include lines for unittests. This uses a slightly modifiedChandler Carruth2017-06-061-1/+1
| | | | | | | | | | | | | | | clang-format (https://reviews.llvm.org/D33932) to keep primary headers at the top and handle new utility headers like 'gmock' consistently with other utility headers. No other change was made. I did no manual edits, all of this is clang-format. This should allow other changes to have more clear and focused diffs, and is especially motivated by moving some headers into more focused libraries. llvm-svn: 304786
* Make mcpu=generic the default for armv7-a and armv8-a.Kristof Beyls2017-06-011-2/+2
| | | | | | | As discussed in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html llvm-svn: 304390
OpenPOWER on IntegriCloud