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* [llvm-mca] Remove unused methods from Backend. NFCAndrea Di Biagio2018-03-161-17/+0
| | | | llvm-svn: 327749
* [llvm-mca] Simplify code. NFC.Andrea Di Biagio2018-03-153-5/+7
| | | | | | | | Now both method DispatchUnit::checkRAT() and DispatchUnit::canDispatch take as input an Instruction refrence instead of an instruction descriptor. This was requested by Simon in D44488 to simplify the diff. llvm-svn: 327640
* [llvm-mca] Remove unused variable from InstrBuilder.cpp. NFCAndrea Di Biagio2018-03-141-1/+0
| | | | | | This was causing a buildbot failure. llvm-svn: 327517
* [llvm-mca] Move the logic that updates the register files from InstrBuilder ↵Andrea Di Biagio2018-03-146-58/+65
| | | | | | | | | | | | | | | | | | | to DispatchUnit. NFCI Before this patch, the register file was always updated at instruction creation time. That means, new read-after-write dependencies, and new temporary registers were allocated at instruction creation time. This patch refactors the code in InstrBuilder, and move all the logic that updates the register file into the dispatch unit. We only want to update the register file when instructions are effectively dispatched (not before). This refactoring also helps removing a bad dependency between the InstrBuilder and the DispatchUnit. No functional change intended. llvm-svn: 327514
* [llvm-mca] Remove the logic that computes the reciprocal throughput, and ↵Andrea Di Biagio2018-03-136-53/+39
| | | | | | | | | | | | | | | | | make the SummaryView independent from the Backend. NFCI Since r327420, the tool can query the MCSchedModel interface to obtain the reciprocal throughput information. As a consequence, method `ResourceManager::getRThroughput`, and method `Backend::getRThroughput` are no longer needed. This patch simplifies the code by removing the custom RThroughput computation. This patch also refactors class SummaryView by removing the dependency with the Backend object. No functional change intended. llvm-svn: 327425
* [llvm-mca] Simplify code that computes the latency of an instruction inAndrea Di Biagio2018-03-131-30/+5
| | | | | | | | | InstrBuilder. NFCI This was possible because of r327406, which added function`computeInstrLatency` to MCSchedModel. llvm-svn: 327415
* [llvm-mca] Use a const ArrayRef in a few places. NFCAndrea Di Biagio2018-03-132-15/+16
| | | | llvm-svn: 327396
* [llvm-mca] Fix unused variable warning in opt mode.Clement Courbet2018-03-131-1/+1
| | | | llvm-svn: 327394
* [llvm-mca] Refactor event listeners to make the backend agnostic to event types.Clement Courbet2018-03-1312-137/+162
| | | | | | | | | | Summary: This is a first step towards making the pipeline configurable. Subscribers: llvm-commits, andreadb Differential Revision: https://reviews.llvm.org/D44309 llvm-svn: 327389
* [llvm-mca] Fix use-of-uninitialized-value error reported by the MemorySanitizer.Andrea Di Biagio2018-03-101-1/+1
| | | | | | This should make the buildbots green again. llvm-svn: 327223
* [llvm-mca] BackendStatistics: early exit from method printSchedulerUsage if theAndrea Di Biagio2018-03-101-0/+9
| | | | | | no scheduler resources were consumed. llvm-svn: 327215
* [llvm-mca] Views are now independent from resource masks. NFCIAndrea Di Biagio2018-03-107-25/+25
| | | | | | | | | This change removes method Backend::getProcResourceMasks() and simplifies some logic in the Views. This effectively removes yet another dependency between the views and the Backend. No functional change intended. llvm-svn: 327214
* [llvm-mca] Move the logic that prints the summary into its own view. NFCIAndrea Di Biagio2018-03-096-91/+193
| | | | llvm-svn: 327128
* [llvm-mca] Run clang-format on the source code. NFCAndrea Di Biagio2018-03-096-24/+28
| | | | llvm-svn: 327125
* [llvm-mca] Fix handling of zero-latency instructions.Andrea Di Biagio2018-03-083-5/+2
| | | | | | | | | | | | | | | | | | | | This patch fixes a problem found when testing zero latency instructions on target AArch64 -mcpu=exynos-m3 / -mcpu=exynos-m1. On Exynos-m3/m1, direct branches are zero-latency instructions that don't consume any processor resources. The DispatchUnit marks zero-latency instructions as "executed", so that no scheduling is required. The event of instruction executed is then notified to all the listeners, and the reorder buffer (managed by the RetireControlUnit) is updated. In particular, the entry associated to the zero-latency instruction in the reorder buffer is marked as executed. Before this patch, the DispatchUnit forgot to assign a retire control unit token (RCUToken) to the zero-latency instruction. As a consequence, the RCUToken was used uninitialized. This was causing a crash in the RetireControlUnit logic. Fixes PR36650. llvm-svn: 327056
* [llvm-mca] add override keyword to method ResourcePressureView::printView().Andrea Di Biagio2018-03-081-1/+1
| | | | | | NFC. llvm-svn: 327027
* [llvm-mca] HWEventListener is a class, not struct.Andrea Di Biagio2018-03-082-2/+2
| | | | | | This should appease the buildbots. llvm-svn: 327025
* [llvm-mca] Unify the API for the various views. NFCIAndrea Di Biagio2018-03-0813-217/+280
| | | | | | | | | | | | | | | This allows the customization of the performance report. Users can specify their own custom sequence of views. Each view contributes a portion of the performance report generated by the BackendPrinter. Internally, class BackendPrinter keeps a sequence of views; views are printed out in sequence when method 'printReport()' is called. This patch addresses one of the two review comments from Clement in D43951. llvm-svn: 327018
* [llvm-mca] Emit the 'Instruction Info' table before the resource pressure view.Andrea Di Biagio2018-03-081-3/+3
| | | | | | | In future, both the summary information and the 'instruction info' table should be moved into a separate "Summary" view. llvm-svn: 327010
* [llvm-mca] LLVM Machine Code Analyzer.Andrea Di Biagio2018-03-0827-0/+5769
llvm-mca is an LLVM based performance analysis tool that can be used to statically measure the performance of code, and to help triage potential problems with target scheduling models. llvm-mca uses information which is already available in LLVM (e.g. scheduling models) to statically measure the performance of machine code in a specific cpu. Performance is measured in terms of throughput as well as processor resource consumption. The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM. The main goal of this tool is not just to predict the performance of the code when run on the target, but also help with diagnosing potential performance issues. Given an assembly code sequence, llvm-mca estimates the IPC (instructions per cycle), as well as hardware resources pressure. The analysis and reporting style were mostly inspired by the IACA tool from Intel. This patch is related to the RFC on llvm-dev visible at this link: http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html Differential Revision: https://reviews.llvm.org/D43951 llvm-svn: 326998
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