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* [llvm-mca] Let the Scheduler notify dispatch stall events caused by the lack ↵Andrea Di Biagio2018-04-114-70/+25
| | | | | | | | | | | | | | | | | | | of scheduling resources. This patch moves part of the logic that notifies dispatch stall events from the DispatchUnit to the Scheduler. The main goal of this patch is to remove (yet another) dependency between the DispatchUnit and the Scheduler. Before this patch, the DispatchUnit had to know about `Scheduler::Event` and how to classify stalls due to the lack of scheduling resources. This patch removes that knowledge and simplifies the logic in DispatchUnit::checkScheduler. This is another change done in preparation for the work to fix PR36663. No functional change intended. llvm-svn: 329835
* Revert "[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS"Andrea Di Biagio2018-04-111-0/+6
| | | | | | It caused a buildbot failure (clang-ppc64le-linux-multistage - build #6424) llvm-svn: 329812
* [llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS.Andrea Di Biagio2018-04-111-6/+0
| | | | llvm-svn: 329807
* [llvm-mca] Minor code cleanup. NFCAndrea Di Biagio2018-04-115-26/+19
| | | | llvm-svn: 329796
* [llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.Andrea Di Biagio2018-04-114-26/+26
| | | | | | Also, removed flag -verbose in favor of flag -retire-stats. llvm-svn: 329794
* [llvm-mca] Move the logic that prints scheduler statistics from ↵Andrea Di Biagio2018-04-116-124/+203
| | | | | | | | BackendStatistics to its own view. Added flag -scheduler-stats to print scheduler related statistics. llvm-svn: 329792
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-04-101-30/+18
| | | | llvm-svn: 329711
* [llvm-mca] Move the logic that prints dispatch unit statistics from ↵Andrea Di Biagio2018-04-106-81/+170
| | | | | | | | | | | BackendStatistics to its own view. This patch moves the logic that collects and analyzes dispatch events to the DispatchStatistics view. Added flag -dispatch-stats to print statistics related to the dispatch logic. llvm-svn: 329708
* [llvm-mca] Increase the default number of iterations to 100.Andrea Di Biagio2018-04-102-2/+2
| | | | llvm-svn: 329694
* Reapply "[llvm-mca] Do not separate iterations with a newline in the ↵Andrea Di Biagio2018-04-102-23/+17
| | | | | | | | timeline view." This reapplies r329403 with a fix for the floating point rounding issue. llvm-svn: 329680
* [llvm-mca] Fix MCACommentConsumerFangrui Song2018-04-091-1/+1
| | | | llvm-svn: 329592
* [llvm-mca] Add the ability to mark regions of code for analysis (PR36875)Andrea Di Biagio2018-04-095-46/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches llvm-mca how to parse code comments in search for special "markers" used to select regions of code. Example: # LLVM-MCA-BEGIN My Code Region .... # LLVM-MCA-END The MCAsmLexer now delegates to an object of class MCACommentParser (i.e. an AsmCommentConsumer) the parsing of code comments to search for begin/end code region markers. A comment starting with substring "LLVM-MCA-BEGIN" marks the beginning of a new region of code. A comment starting with substring "LLVM-MCA-END" marks the end of the last region. This implementation doesn't allow regions to overlap. Each region can have a optional description; internally, each region is identified by a range of source code locations (SMLoc). MCInst objects are added to a region R only if the source location for the MCInst is in the range of locations specified by R. By default, the tool allocates an implicit "Default" code region which contains every source location. See new tests llvm-mca-marker-*.s for a few examples. A new Backend object is created for every region. So, the analysis is conducted on every parsed code region. The final report is the union of the reports generated for every code region. Note that empty regions are skipped. Special "[#] Code Region - ..." strings are used in the report to mark the portion which is specific to a code region only. For example, see llvm-mca-markers-5.s. Differential Revision: https://reviews.llvm.org/D45433 llvm-svn: 329590
* Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the ↵Hans Wennborg2018-04-091-1/+1
| | | | | | | | | | | | timeline view." This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251 > Also, update a few tests to minimize the diff in D45369. > No functional change intended. llvm-svn: 329569
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-04-081-33/+26
| | | | llvm-svn: 329532
* [llvm-mca] Do not separate iterations with a newline in the timeline view.Andrea Di Biagio2018-04-061-1/+1
| | | | | | | Also, update a few tests to minimize the diff in D45369. No functional change intended. llvm-svn: 329403
* [documentation][llvm-mca] Update the documentation.Andrea Di Biagio2018-04-051-34/+14
| | | | | | | Scheduling models can now describe processor register files and retire control units. This updates the existing documentation and the README file. llvm-svn: 329311
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-053-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [llvm-mca] Remove flag -max-retire-per-cycle, and update the docs.Andrea Di Biagio2018-04-053-16/+10
| | | | | | | | This is done in preparation for D45259. With D45259, models can specify the size of the reorder buffer, and the retire throughput directly via tablegen. llvm-svn: 329274
* [llvm-mca] Move the logic that prints register file statistics to its own ↵Andrea Di Biagio2018-04-036-97/+186
| | | | | | | | | | | | | view. NFCI Before this patch, the "BackendStatistics" view was responsible for printing the register file usage (as well as many other statistics). Now users can enable register file usage statistics using the command line flag `-register-file-stats`. By default, the tool doesn't print register file statistics. llvm-svn: 329083
* [llvm-mca] Remove redundant include from BackendStatistics.h. NFCAndrea Di Biagio2018-04-031-3/+2
| | | | | | Also use llvm::DenseMap for Histograms (instead of std::map). llvm-svn: 329074
* [MC][Tablegen] Allow the definition of processor register files in the ↵Andrea Di Biagio2018-04-035-88/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling model for llvm-mca This patch allows the description of register files in processor scheduling models. This addresses PR36662. A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td. Targets can optionally describe register files for their processors using that class. In particular, class RegisterFile allows to specify: - The total number of physical registers. - Which target registers are accessible through the register file. - The cost of allocating a register at register renaming stage. Example (from this patch - see file X86/X86ScheduleBtVer2.td) def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]> Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register. The syntax allows to specify an empty set of register classes. An empty set of register classes means: this register file models all the registers specified by the Target. For each register class, users can specify an optional register cost. By default, register costs default to 1. A value of 0 for the number of physical registers means: "this register file has an unbounded number of physical registers". This patch is structured in two parts. * Part 1 - MC/Tablegen * A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files. Information about register files is accessible through an instance of MCExtraProcessorInfo. The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers. I think that this design would make easier for targets to get rid of the extra processor information if they don't want it. * Part 2 - llvm-mca related * The second part of this patch is related to changes to llvm-mca. The main differences are: 1) class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage. 2) Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction. 3) The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor. The effect of point 3. is also visible in tests register-files-[1..5].s. Differential Revision: https://reviews.llvm.org/D44980 llvm-svn: 329067
* [llvm-mca] Do not assume that implicit reads cannot be associated with ↵Andrea Di Biagio2018-04-022-9/+20
| | | | | | | | | | ReadAdvance entries. Before, the instruction builder incorrectly assumed that only explicit reads could have been associated with ReadAdvance entries. This patch fixes the issue and adds a test to verify it. llvm-svn: 328972
* [tools] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-011-10/+10
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: JDevlieghere, zturner, echristo, dberris, friss Reviewed By: echristo Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D45141 llvm-svn: 328943
* [llvm-mca] Correctly set the ReadAdvance information for register use operands.Andrea Di Biagio2018-03-296-37/+87
| | | | | | | | | | | | The tool was passing the wrong operand index to method MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and not the operand index. This was found when testing X86 code where instructions had a memory folded operand. This patch fixes the issue and adds test read-advance-1.s to ensure that the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used. llvm-svn: 328790
* [llvm-mca] pass the correct set of used registers in checkRAT.Andrea Di Biagio2018-03-271-3/+5
| | | | | | | | | We were incorrectly initializing the array of used registers in method checkRAT. As a consequence, the number of register file stalls was misreported. Added a test to cover this case. llvm-svn: 328629
* [llvm-mca] Fix how views are added to the InstructionTables.Andrea Di Biagio2018-03-263-14/+20
| | | | | | | This should fix the stack-use-after-scope reported by the asan buildbots after revision 328493. llvm-svn: 328499
* [llvm-mca] Add a flag -instruction-info to enable/disable the instruction ↵Andrea Di Biagio2018-03-261-4/+14
| | | | | | info view. llvm-svn: 328493
* [llvm-mca] Add flag -instruction-tables to print the theoretical resource ↵Andrea Di Biagio2018-03-265-1/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pressure distribution for instructions (PR36874) The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
* [llvm-mca] run clang-format on all files.Andrea Di Biagio2018-03-2419-30/+17
| | | | | | This also addresses Simon's review comment in D44839. llvm-svn: 328428
* [llvm-mca] Remove unused field in InstrBuilder. NFCAndrea Di Biagio2018-03-241-1/+0
| | | | llvm-svn: 328427
* [llvm-mca] Split the InstructionInfoView from the SummaryView.Andrea Di Biagio2018-03-236-106/+155
| | | | llvm-svn: 328358
* [llvm-mca] update the ResourcePressureView after r328335. NFC.Andrea Di Biagio2018-03-232-8/+8
| | | | | | This should have been part of r328335. I forgot to svn add these files. llvm-svn: 328340
* [llvm-mca] Make the resource cost a double.Andrea Di Biagio2018-03-233-9/+10
| | | | | | | | This is done in preparation for the fix for PR36874. The number of cycles consumed for each pipe is now a double quantity. This allows reuse of the resource pressure view to print out instruction tables. llvm-svn: 328335
* [llvm-mca] Pass the InstrBuilder to the constructor of Backend.Andrea Di Biagio2018-03-233-8/+10
| | | | | | | This is done in preparation for the fix for PR36784. No functional change. llvm-svn: 328306
* [llvm-mca] Add flag -resource-pressure to enable/disable printing of the ↵Andrea Di Biagio2018-03-231-1/+7
| | | | | | | | | resource pressure view. By default, the tool always enables the resource pressure view. This flag lets user specify whether they want to add that view or not. llvm-svn: 328305
* [llvm-mca] Minor refactoring. NFCIAndrea Di Biagio2018-03-225-28/+31
| | | | | | Also, removed a couple of unused methods from class Instruction. llvm-svn: 328198
* [llvm-mca] Simplify (and better standardize) the Instruction interface.Andrea Di Biagio2018-03-226-31/+29
| | | | llvm-svn: 328190
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-03-2211-85/+69
| | | | llvm-svn: 328187
* [llvm-mca] Move the logic that computes the register file usage to the ↵Andrea Di Biagio2018-03-217-75/+103
| | | | | | | | | | | | | | | | | | | | | | | BackendStatistics view. With this patch, the "instruction dispatched" event now provides information related to the number of microarchitectural registers used in each register file. Similarly, the "instruction retired" event is now able to tell how may registers are freed in each register file. Currently, the BackendStatistics view is the only consumer of register usage/pressure information. BackendStatistics uses that info to print out a few general statistics (i.e. max number of mappings used; total mapping created). Before this patch, the BackendStatistics was forced to query the Backend to obtain the register pressure information. This helps removes that dependency. Now views are completely independent from the Backend. As a consequence, it should be easier to address PR36663 and further modularize the pipeline. Added a couple of test cases in the BtVer2 specific directory. llvm-svn: 328129
* [llvm-mca] Clean up some code. NFCAndrea Di Biagio2018-03-212-15/+4
| | | | | | Removed a couple of methods from DispatchUnit. llvm-svn: 328094
* [llvm-mca] add keyword override to a couple of methods in BackendStatistics.Andrea Di Biagio2018-03-201-2/+2
| | | | | | This should fix the buildbots after r328011. llvm-svn: 328029
* [llvm-mca] Remove const from a bunch of ArrayRef. NFCAndrea Di Biagio2018-03-206-14/+14
| | | | llvm-svn: 328018
* [llvm-mca] Move the logic that computes the scheduler's queue usage to the ↵Andrea Di Biagio2018-03-207-59/+119
| | | | | | | | | | | | | | | | | | | | | | BackendStatistics view. This patch introduces two new callbacks in the event listener interface to handle the "buffered resource reserved" event and the "buffered resource released" event. Every time a buffered resource is used, an event is generated. Before this patch, the Scheduler (with the help of the ResourceManager) was responsible for tracking the scheduler's queue usage. However, that design forced the Scheduler to 'publish' scheduler's queue pressure information through the Backend interface. The goal of this patch is to break the dependency between the BackendStatistics view, and the Backend. Now the Scheduler knows how to notify "buffer reserved/released" events. The scheduler's queue usage analysis has been moved to the BackendStatistics. Differential Revision: https://reviews.llvm.org/D44686 llvm-svn: 328011
* [llvm-mca] Use llvm::make_unique in a few places. NFCAndrea Di Biagio2018-03-204-23/+19
| | | | | | Also, clang-format a couple of DEBUG functions. llvm-svn: 327978
* [llvm-mca] Move the routine that computes processor resource masks to its ↵Andrea Di Biagio2018-03-209-89/+137
| | | | | | | | | | | | | | | | | | own file. Function computeProcResourceMasks is used by the ResourceManager (owned by the Scheduler) to compute resource masks for processor resources. Before this refactoring, there was an implicit dependency between the Scheduler and the InstrBuilder. That is because InstrBuilder has to know about resource masks when computing the set of processor resources consumed by a new instruction. With this patch, the functionality that computes resource masks has been extracted from the ResourceManager, and moved to a separate file (Support.h). This helps removing the dependency between the Scheduler and the InstrBuilder. No functional change intended. llvm-svn: 327973
* [llvm-mca] Remove unused method from ResourceManager. NFCAndrea Di Biagio2018-03-191-2/+0
| | | | llvm-svn: 327888
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-03-193-48/+51
| | | | llvm-svn: 327886
* [llvm-mca] Add pipeline stall events.Andrea Di Biagio2018-03-197-118/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new class named HWStallEvent (see HWEventListener.h), and updates the event listener interface. A HWStallEvent represents a pipeline stall caused by the lack of hardware resources. Similarly to HWInstructionEvent, the event type is an unsigned, and the exact meaning depends on the subtarget. At the moment, HWStallEvent supports a few generic dispatch events. The main goals of this patch is to remove the logic that counts dispatch stalls from the DispatchUnit to the BackendStatistics view. Previously, DispatchUnit was responsible for counting and classifying dispatch stall events. With this patch, we delegate the task of counting and classifying stall events to the listeners (i.e. in our case, it is view "BackendStatistics"). So, the DispatchUnit doesn't have to do extra (unnecessary) bookkeeping. This patch also helps futher simplifying the Backend interface. Now class BackendStatistics no longer has to query the Backend interface to obtain the number of dispatch stalls. As a consequence, we can get rid of all the 'getNumXXX()' methods from class Backend. The long term goal is to remove all the remaining dependencies between the Backend and the BackendStatistics interface. Differential Revision: https://reviews.llvm.org/D44621 llvm-svn: 327837
* [llvm-mca] Allow the definition of multiple register files.Andrea Di Biagio2018-03-182-100/+249
| | | | | | | | | | | | | | | | | | | | This is a refactoring in preparation for other two changes that will allow scheduling models to define multiple register files. This is the first step towards fixing PR36662. class RegisterFile (in Dispatch.h) now can emulate multiple register files. Internally, it tracks the number of available physical registers in each register file (described by class RegisterFileInfo). Each register file is associated to a list of MCRegisterClass indices. Knowing the register class indices allows to map physical registers to register files. The long term goal is to allow processor models to optionally specify how many register files are implemented via tablegen. Differential Revision: https://reviews.llvm.org/D44488 llvm-svn: 327798
* [llvm-mca] Remove method getSchedModel() from the Backend.Andrea Di Biagio2018-03-163-7/+7
| | | | llvm-svn: 327756
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