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* [llvm-mca] removes flag -instruction-tables from the "View Options" category.Andrea Di Biagio2018-05-051-25/+15
| | | | | | | | This patch also improves the description of a couple of flags in the view options. With this change, the -help now specifies which views are enabled by default. llvm-svn: 331594
* [llvm-mca] minor tweak to the resource pressure printing functionality. NFC.Andrea Di Biagio2018-05-051-1/+1
| | | | llvm-svn: 331590
* [llvm-mca] Add descriptive names for the TimelineView report characters. NFC.Matt Davis2018-05-042-8/+18
| | | | | | | | | | | | | | | | Summary: This change makes the TimelineView source simpler to read and easier to modify in the future. This patch introduces a class of static chars used as the display values in the TimelineView report, this change just eliminates a few magic characters. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46409 llvm-svn: 331540
* [llvm-mca] use colors for warnings and notes generated by InstrBuilder.Andrea Di Biagio2018-05-042-10/+10
| | | | llvm-svn: 331517
* [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.Andrea Di Biagio2018-05-044-11/+13
| | | | | | | | | We don't need to pass the instruction index to the method that constructs new instruction descriptors. No functional change intended. llvm-svn: 331516
* [llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch ↵Matt Davis2018-05-015-132/+175
| | | | | | | | | | translation unit into its own translation unit. NFC The logic remains the same. Eventually, I see the RCU acting as its own separate stage in the instruction pipeline. Differential Revision: https://reviews.llvm.org/D46331 llvm-svn: 331316
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-0111-20/+20
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.Andrea Di Biagio2018-04-302-2/+4
| | | | | | | | | | | | | | | | This fixes PR37293. We can have scheduling classes with no write latency entries, that still consume processor resources. We don't want to treat those instructions as zero-latency instructions; they still have to be issued to the underlying pipelines, so they still consume resource cycles. This is likely to be a regression which I have accidentally introduced at revision 330807. Now, if an instruction has a non-empty set of write processor resources, we conservatively treat it as a normal (i.e. non zero-latency) instruction. llvm-svn: 331193
* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-301-1/+1
| | | | | | | | | Added Intel Atom tests to verify that the tool correctly generates instruction tables even if the CPU is in-order. Fixes PR37282. llvm-svn: 331169
* [MCA] [NFC] Remove unused Index formal from ResourceManager::issueInstructionMatt Davis2018-04-262-3/+3
| | | | | | | | | | | | | | Summary: The instruction index was never referenced in the body. Just a minor cleanup. Reviewers: andreadb Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46142 llvm-svn: 331001
* [llvm-mca] Make ViewOptions static. NFCIFilipe Cabecinhas2018-04-251-1/+1
| | | | llvm-svn: 330829
* [llvm-mca] Add a new option category for views.Andrea Di Biagio2018-04-251-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | With this patch, options to add/tweak views are all grouped together in the -help output. The new "View Options" category looks like this: ``` View Options: -dispatch-stats - Print dispatch statistics -instruction-info - Print the instruction info view -instruction-tables - Print instruction tables -register-file-stats - Print register file statistics -resource-pressure - Print the resource pressure view -retire-stats - Print retire control unit statistics -scheduler-stats - Print scheduler statistics -timeline - Print the timeline view -timeline-max-cycles=<uint> - Maximum number of cycles in the timeline view. Defaults to 80 cycles -timeline-max-iterations=<uint> - Maximum number of iterations to print in timeline view ``` llvm-svn: 330816
* [llvm-mca] run clang-format on a bunch of files. NFCAndrea Di Biagio2018-04-254-14/+13
| | | | llvm-svn: 330811
* [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.Andrea Di Biagio2018-04-251-2/+7
| | | | llvm-svn: 330809
* [llvm-mca] Remove method Instruction::isZeroLatency(). NFCIAndrea Di Biagio2018-04-255-13/+11
| | | | llvm-svn: 330807
* [llvm-mca] Remove unused flag -verbose. NFCAndrea Di Biagio2018-04-241-4/+0
| | | | | | I forgot to remove it at r329794. llvm-svn: 330757
* [llvm-mca] Default the output asm dialect used by the instruction printer to ↵Andrea Di Biagio2018-04-241-12/+16
| | | | | | | | | | | | | | | | the input asm dialect. The instruction printer used by llvm-mca to generate the performance report now defaults the output assembly format to the format used for the input assembly file. On x86, the asm format can be either AT&T or Intel, depending on the presence/absence of directive `.intel_syntax`. Users can still specify a different assembly dialect with the command line flag -output-asm-variant=<uint>. llvm-svn: 330733
* [llvm-mca] Refactor the Scheduler interface in preparation for PR36663.Andrea Di Biagio2018-04-242-79/+107
| | | | | | | | | | | | | Zero latency instructions are now scheduled the same way as other instructions. Before this patch, there was a specialzed code path for those instructions. All scheduler events are now generated from method `scheduleInstruction()` and from method `cycleEvent()`. This will make easier to implement a "execution stage", and let that stage publish all the scheduler events. No functional change intended. llvm-svn: 330723
* [llvm-mca] Use WithColor for printing errorsJonas Devlieghere2018-04-181-12/+15
| | | | | | | | Use convenience helpers in WithColor to print errors and notes. Differential revision: https://reviews.llvm.org/D45666 llvm-svn: 330267
* Define InitLLVM to do common initialization all at once.Rui Ueyama2018-04-131-5/+2
| | | | | | | | | | | We have a few functions that virtually all command wants to run on process startup/shutdown. This patch adds InitLLVM class to do that all at once, so that we don't need to copy-n-paste boilerplate code to each llvm command's main() function. Differential Revision: https://reviews.llvm.org/D45602 llvm-svn: 330046
* [llvm-mca] Ensure that instructions with a schedule read-advance are always ↵Andrea Di Biagio2018-04-132-57/+47
| | | | | | | | | | | | | | issued in the right order. Normally, the Scheduler prioritizes older instructions over younger instructions during the instruction issue stage. In one particular case where a dependent instruction had a schedule read-advance associated to one of the input operands, this rule was not correctly applied. This patch fixes the issue and adds a test to verify that we don't regress that particular case. llvm-svn: 330032
* [llvm-mca] Removed unused argument from cycleEvent. NFCAndrea Di Biagio2018-04-1210-17/+17
| | | | llvm-svn: 329895
* [llvm-mca] Let the Scheduler notify dispatch stall events caused by the lack ↵Andrea Di Biagio2018-04-114-70/+25
| | | | | | | | | | | | | | | | | | | of scheduling resources. This patch moves part of the logic that notifies dispatch stall events from the DispatchUnit to the Scheduler. The main goal of this patch is to remove (yet another) dependency between the DispatchUnit and the Scheduler. Before this patch, the DispatchUnit had to know about `Scheduler::Event` and how to classify stalls due to the lack of scheduling resources. This patch removes that knowledge and simplifies the logic in DispatchUnit::checkScheduler. This is another change done in preparation for the work to fix PR36663. No functional change intended. llvm-svn: 329835
* Revert "[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS"Andrea Di Biagio2018-04-111-0/+6
| | | | | | It caused a buildbot failure (clang-ppc64le-linux-multistage - build #6424) llvm-svn: 329812
* [llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS.Andrea Di Biagio2018-04-111-6/+0
| | | | llvm-svn: 329807
* [llvm-mca] Minor code cleanup. NFCAndrea Di Biagio2018-04-115-26/+19
| | | | llvm-svn: 329796
* [llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.Andrea Di Biagio2018-04-114-26/+26
| | | | | | Also, removed flag -verbose in favor of flag -retire-stats. llvm-svn: 329794
* [llvm-mca] Move the logic that prints scheduler statistics from ↵Andrea Di Biagio2018-04-116-124/+203
| | | | | | | | BackendStatistics to its own view. Added flag -scheduler-stats to print scheduler related statistics. llvm-svn: 329792
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-04-101-30/+18
| | | | llvm-svn: 329711
* [llvm-mca] Move the logic that prints dispatch unit statistics from ↵Andrea Di Biagio2018-04-106-81/+170
| | | | | | | | | | | BackendStatistics to its own view. This patch moves the logic that collects and analyzes dispatch events to the DispatchStatistics view. Added flag -dispatch-stats to print statistics related to the dispatch logic. llvm-svn: 329708
* [llvm-mca] Increase the default number of iterations to 100.Andrea Di Biagio2018-04-102-2/+2
| | | | llvm-svn: 329694
* Reapply "[llvm-mca] Do not separate iterations with a newline in the ↵Andrea Di Biagio2018-04-102-23/+17
| | | | | | | | timeline view." This reapplies r329403 with a fix for the floating point rounding issue. llvm-svn: 329680
* [llvm-mca] Fix MCACommentConsumerFangrui Song2018-04-091-1/+1
| | | | llvm-svn: 329592
* [llvm-mca] Add the ability to mark regions of code for analysis (PR36875)Andrea Di Biagio2018-04-095-46/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches llvm-mca how to parse code comments in search for special "markers" used to select regions of code. Example: # LLVM-MCA-BEGIN My Code Region .... # LLVM-MCA-END The MCAsmLexer now delegates to an object of class MCACommentParser (i.e. an AsmCommentConsumer) the parsing of code comments to search for begin/end code region markers. A comment starting with substring "LLVM-MCA-BEGIN" marks the beginning of a new region of code. A comment starting with substring "LLVM-MCA-END" marks the end of the last region. This implementation doesn't allow regions to overlap. Each region can have a optional description; internally, each region is identified by a range of source code locations (SMLoc). MCInst objects are added to a region R only if the source location for the MCInst is in the range of locations specified by R. By default, the tool allocates an implicit "Default" code region which contains every source location. See new tests llvm-mca-marker-*.s for a few examples. A new Backend object is created for every region. So, the analysis is conducted on every parsed code region. The final report is the union of the reports generated for every code region. Note that empty regions are skipped. Special "[#] Code Region - ..." strings are used in the report to mark the portion which is specific to a code region only. For example, see llvm-mca-markers-5.s. Differential Revision: https://reviews.llvm.org/D45433 llvm-svn: 329590
* Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the ↵Hans Wennborg2018-04-091-1/+1
| | | | | | | | | | | | timeline view." This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251 > Also, update a few tests to minimize the diff in D45369. > No functional change intended. llvm-svn: 329569
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-04-081-33/+26
| | | | llvm-svn: 329532
* [llvm-mca] Do not separate iterations with a newline in the timeline view.Andrea Di Biagio2018-04-061-1/+1
| | | | | | | Also, update a few tests to minimize the diff in D45369. No functional change intended. llvm-svn: 329403
* [documentation][llvm-mca] Update the documentation.Andrea Di Biagio2018-04-051-34/+14
| | | | | | | Scheduling models can now describe processor register files and retire control units. This updates the existing documentation and the README file. llvm-svn: 329311
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-053-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [llvm-mca] Remove flag -max-retire-per-cycle, and update the docs.Andrea Di Biagio2018-04-053-16/+10
| | | | | | | | This is done in preparation for D45259. With D45259, models can specify the size of the reorder buffer, and the retire throughput directly via tablegen. llvm-svn: 329274
* [llvm-mca] Move the logic that prints register file statistics to its own ↵Andrea Di Biagio2018-04-036-97/+186
| | | | | | | | | | | | | view. NFCI Before this patch, the "BackendStatistics" view was responsible for printing the register file usage (as well as many other statistics). Now users can enable register file usage statistics using the command line flag `-register-file-stats`. By default, the tool doesn't print register file statistics. llvm-svn: 329083
* [llvm-mca] Remove redundant include from BackendStatistics.h. NFCAndrea Di Biagio2018-04-031-3/+2
| | | | | | Also use llvm::DenseMap for Histograms (instead of std::map). llvm-svn: 329074
* [MC][Tablegen] Allow the definition of processor register files in the ↵Andrea Di Biagio2018-04-035-88/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scheduling model for llvm-mca This patch allows the description of register files in processor scheduling models. This addresses PR36662. A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td. Targets can optionally describe register files for their processors using that class. In particular, class RegisterFile allows to specify: - The total number of physical registers. - Which target registers are accessible through the register file. - The cost of allocating a register at register renaming stage. Example (from this patch - see file X86/X86ScheduleBtVer2.td) def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]> Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register. The syntax allows to specify an empty set of register classes. An empty set of register classes means: this register file models all the registers specified by the Target. For each register class, users can specify an optional register cost. By default, register costs default to 1. A value of 0 for the number of physical registers means: "this register file has an unbounded number of physical registers". This patch is structured in two parts. * Part 1 - MC/Tablegen * A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files. Information about register files is accessible through an instance of MCExtraProcessorInfo. The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers. I think that this design would make easier for targets to get rid of the extra processor information if they don't want it. * Part 2 - llvm-mca related * The second part of this patch is related to changes to llvm-mca. The main differences are: 1) class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage. 2) Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction. 3) The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor. The effect of point 3. is also visible in tests register-files-[1..5].s. Differential Revision: https://reviews.llvm.org/D44980 llvm-svn: 329067
* [llvm-mca] Do not assume that implicit reads cannot be associated with ↵Andrea Di Biagio2018-04-022-9/+20
| | | | | | | | | | ReadAdvance entries. Before, the instruction builder incorrectly assumed that only explicit reads could have been associated with ReadAdvance entries. This patch fixes the issue and adds a test to verify it. llvm-svn: 328972
* [tools] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-011-10/+10
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: JDevlieghere, zturner, echristo, dberris, friss Reviewed By: echristo Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D45141 llvm-svn: 328943
* [llvm-mca] Correctly set the ReadAdvance information for register use operands.Andrea Di Biagio2018-03-296-37/+87
| | | | | | | | | | | | The tool was passing the wrong operand index to method MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and not the operand index. This was found when testing X86 code where instructions had a memory folded operand. This patch fixes the issue and adds test read-advance-1.s to ensure that the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used. llvm-svn: 328790
* [llvm-mca] pass the correct set of used registers in checkRAT.Andrea Di Biagio2018-03-271-3/+5
| | | | | | | | | We were incorrectly initializing the array of used registers in method checkRAT. As a consequence, the number of register file stalls was misreported. Added a test to cover this case. llvm-svn: 328629
* [llvm-mca] Fix how views are added to the InstructionTables.Andrea Di Biagio2018-03-263-14/+20
| | | | | | | This should fix the stack-use-after-scope reported by the asan buildbots after revision 328493. llvm-svn: 328499
* [llvm-mca] Add a flag -instruction-info to enable/disable the instruction ↵Andrea Di Biagio2018-03-261-4/+14
| | | | | | info view. llvm-svn: 328493
* [llvm-mca] Add flag -instruction-tables to print the theoretical resource ↵Andrea Di Biagio2018-03-265-1/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pressure distribution for instructions (PR36874) The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
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