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* [llvm-mca] use APint::operator[] to obtain the bit value. NFCAndrea Di Biagio2018-06-201-4/+2
| | | | llvm-svn: 335131
* [llvm-mca][X86] Teach how to identify register writes that implicitly clear ↵Andrea Di Biagio2018-06-205-33/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | the upper portion of a super-register. This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113
* [llvm-mca] Cleanup the header syntax line. Fix a comment. NFC.Matt Davis2018-06-181-3/+2
| | | | | | This patch removes a few dashes from the header comment to make room for the syntax line. llvm-svn: 334986
* [llvm-mca] Use an ordered map to collect hardware statistics. NFC.Andrea Di Biagio2018-06-184-9/+11
| | | | | | | Histogram entries are now ordered by key. This should improves their readability when statistics are printed. llvm-svn: 334961
* [MCA] Add -summary-view optionRoman Lebedev2018-06-151-1/+10
| | | | | | | | | | | | | | | | | | | Summary: While that is indeed a quite interesting summary stat, there are cases where it does not really add anything other than consuming extra lines. Declutters the output of D48190. Reviewers: RKSimon, andreadb, courbet, craig.topper Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48209 llvm-svn: 334833
* [llvm-mca] Clean up the header comment. NFC.Matt Davis2018-06-142-4/+2
| | | | | | This change removes a few dashes to make room for the header syntax string. llvm-svn: 334770
* [llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class).Matt Davis2018-06-149-213/+397
| | | | | | | | | | | | | | Summary: This patch transforms the Scheduler class into the ExecuteStage. Most of the logic remains. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47246 llvm-svn: 334679
* [llvm-mca] Fixed a bug in the logic that checks if a memory operation is ↵Andrea Di Biagio2018-06-131-8/+12
| | | | | | | | | | | | | | | ready to execute. Fixes PR37790. In some (very rare) cases, the LSUnit (Load/Store unit) was wrongly marking a load (or store) as "ready to execute" effectively bypassing older memory barrier instructions. To reproduce this bug, the memory barrier must be the first instruction in the input assembly sequence, and it doesn't have to perform any register writes. llvm-svn: 334633
* Revert: [llvm-mca] Flush the output stream before we start the analysis of a ↵Andrea Di Biagio2018-06-131-1/+0
| | | | | | | | | new code region. NFC Not sure why, but it breaks buildbot clang-cmake-armv8-full. It causes a failure in TEST 'Xray-armhf-linux :: TestCases/Posix/profiling-single-threaded.cc'. llvm-svn: 334617
* [llvm-mca] Flush the output stream before we start the analysis of a new ↵Andrea Di Biagio2018-06-131-0/+1
| | | | | | code region. NFC llvm-svn: 334610
* [llvm-mca] Correctly update the CyclesLeft of a register read in the ↵Andrea Di Biagio2018-06-052-7/+20
| | | | | | | | | | | presence of partial register updates. This patch fixe the logic in ReadState::cycleEvent(). That method was not correctly updating field `TotalCycles`. Added extra code comments in class ReadState to better describe each field. llvm-svn: 334028
* [RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.Andrea Di Biagio2018-06-043-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | This patch is the last of a sequence of three patches related to LLVM-dev RFC "MC support for variant scheduling classes". http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html This fixes PR36672. The main goal of this patch is to teach llvm-mca how to solve variant scheduling classes. This patch does that, plus it adds new variant scheduling classes to the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called dependency breaking instructions that are known to generate zero, and that are optimized out in hardware at register renaming stage). Without the BtVer2 change, this patch would not have had any meaningful tests. This patch is effectively the union of two changes: 1) a change that teaches llvm-mca how to resolve variant scheduling classes. 2) a change to the BtVer2 scheduling model that allows us to special-case packed XOR zero-idioms (this partially fixes PR36671). Differential Revision: https://reviews.llvm.org/D47374 llvm-svn: 333909
* [llvm-mca] Track cycles contributed by resources that are in a 'Super' ↵Andrea Di Biagio2018-06-041-1/+19
| | | | | | | | | | | | | | relationship. This is required if we want to correctly match the behavior of method SubtargetEmitter::ExpandProcResource() in Tablegen. When computing the set of "consumed" processor resources and resource cycles, the logic in ExpandProcResource() doesn't update the number of resource cycles contributed by a "Super" resource to a group. We need to take this into account when a model declares a processor resource which is part of a 'processor resource group', and it is also used as the "Super" of other resources. llvm-svn: 333892
* [llvm-mca] Move the logic that computes the block throughput into Support.h. NFCAndrea Di Biagio2018-06-014-48/+63
| | | | | | | This will allow us to share the logic that computes the block throughput with other views. llvm-svn: 333755
* [llvm-mca] Fixed a problem caused by an invalid use of a processor resource ↵Andrea Di Biagio2018-05-311-9/+7
| | | | | | | | | | | | | mask in the Scheduler. The lambda functions used by method ResourceManager::mustIssueImmediately() was incorrectly truncating masks of buffered processor resources to 32-bit quantities. The invalid mask values were then used to access a map of processor resource descriptors. Fixes PR37643. llvm-svn: 333692
* [llvm-mca] Update the header's guard name. NFC.Matt Davis2018-05-251-3/+3
| | | | | | This patch also places a comment at the end of the header guard. llvm-svn: 333297
* [llvm-mca] Update DispatchStage header comment. NFC.Matt Davis2018-05-252-3/+10
| | | | | | Updated the comment to be a wee bit more descriptive. llvm-svn: 333296
* [llvm-mca] Add the RetireStage. Matt Davis2018-05-2511-82/+175
| | | | | | | | | | | | | | | | | Summary: This class maintains the same logic as the original RetireControlUnit. This is just an intermediate patch to make the RCU a Stage. Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb, courbet Subscribers: javed.absar, mgorny, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47244 llvm-svn: 333292
* [llvm-mca] Fix a rounding problem in SummaryView.cpp exposed by r333204.Andrea Di Biagio2018-05-241-4/+7
| | | | | | | | Before printing the block reciprocal throughput, ensure that the floating point number is always rounded the same way on every target. No functional change intended. llvm-svn: 333210
* [llvm-mca] Fix header comments. NFC.Matt Davis2018-05-232-2/+2
| | | | llvm-svn: 333096
* [llvm-mca] Print the "Block RThroughput" in the SummaryView.Andrea Di Biagio2018-05-233-14/+99
| | | | | | | | | | | | | | | | | | | This patch implements the "block reciprocal throughput" computation in the SummaryView. The block reciprocal throughput is computed as the MAX of: - NumMicroOps / DispatchWidth - Resource Cycles / #Units (for every resource consumed). The block throughput is bounded from above by the hardware dispatch throughput. That is because the DispatchWidth is an upper bound on how many opcodes can be part of a single dispatch group. The block throughput is also limited by the amount of hardware parallelism. The number of available resource units affects how the resource pressure is distributed, and also how many blocks can be delivered every cycle. llvm-svn: 333095
* [llvm-mca] Move DispatchStage::cycleEvent to preExecute. NFC.Matt Davis2018-05-223-10/+10
| | | | | | | | | | | | | | | | | | | | | | | Summary: This is an intermediate change, it moves the non-notification logic from Backend::notifyCycleBegin to runCycle(). Once the scheduler becomes part of the Execution stage the explicit call to Scheduler::cycleEvent will disappear. The logic for Dispatch::cycleEvent() can be in the preExecute phase, which this patch addresses. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47213 llvm-svn: 333029
* [llvm-mca] Removed an empty line generated by the timeline view. NFC.Andrea Di Biagio2018-05-211-7/+10
| | | | | | Also, regenerate all tests. llvm-svn: 332853
* [llvm-mca] Make Dispatch a subclass of Stage.Matt Davis2018-05-1711-130/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The logic of dispatch remains the same, but now DispatchUnit is a Stage (DispatchStage). This change has the benefit of simplifying the backend runCycle() code. The same logic applies, but it belongs to different components now. This is just a start, eventually we will need to remove the call to the DispatchStage in Scheduler.cpp, but that will be a separate patch. This change is mostly a renaming and moving of existing logic. This change also encouraged me to remove the Subtarget (STI) member from the Backend class. That member was used to initialize the other members of Backend and to eventually call DispatchUnit::dispatch(). Now that we have Stages, we can eliminate this by instantiating the DispatchStage with everything it needs at the time of construction (e.g., Subtarget). That change allows us to call DispatchStage::execute(IR) as we expect to call execute() for all other stages. Once we add the Stage list (D46907) we can more cleanly call preExecute() on all of the stages, DispatchStage, will probably wrap cycleEvent() in that case. Made some formatting and minor cleanups to README.txt. Some of the text was re-flowed to stay within 80 cols. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb, courbet Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46983 llvm-svn: 332652
* [llvm-mca] Hide unrelated flags from the -help output.Andrea Di Biagio2018-05-171-23/+35
| | | | llvm-svn: 332615
* [llvm-mca] add flag -all-views and flag -all-stats.Andrea Di Biagio2018-05-171-0/+38
| | | | | | | Flag -all-views enables all the views. Flag -all-stats enables all the views that print hardware statistics. llvm-svn: 332602
* [llvm-mca] Move the RegisterFile class into its own translation unit. NFCMatt Davis2018-05-165-371/+428
| | | | | | | | | | | | | | Summary: This change will help us turn the DispatchUnit into its own stage. Reviewers: andreadb, RKSimon, courbet Reviewed By: andreadb, courbet Subscribers: mgorny, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46916 llvm-svn: 332493
* [llvm-mca] Move definitions in FetchStage.cpp inside namespace mca. NFCAndrea Di Biagio2018-05-162-3/+3
| | | | | | Also, get rid of a redundant include in FetchStage.h and FetchStage.cpp. llvm-svn: 332468
* [llvm-mca] Fix perf regression after r332390.Andrea Di Biagio2018-05-162-7/+9
| | | | | | | | | | | | | | | | | | | | | | | Revision 332390 introduced a FetchStage class in llvm-mca. By design, FetchStage owns all the instructions in-flight in the OoO Backend. Before this change, new instructions were added to a DenseMap indexed by instruction id. The problem with using a DenseMap is that elements are not ordered by key. This was causing a massive slow down in method FetchStage::postExecute(), which searches for instructions retired that can be deleted. This patch replaces the DenseMap with a std::map ordered by instruction index. At the end of every cycle, we search for the first instruction which is not marked as "retired", and we remove all the previous instructions before it. This works well because instructions are retired in-order. Before this patch, a debug build of llvm-mca (on my Ryzen linux machine) took ~8.0 seconds to simulate 3000 iterations of a x86 dot-product (a `vmulps, vpermilps, vaddps, vpermilps, vaddps` sequence). With this patch, it now takes ~0.8s to run all the 3000 iterations. llvm-svn: 332461
* [llvm-mca] Remove redundant includes in Stage.h.Andrea Di Biagio2018-05-164-9/+8
| | | | | | | | This patch also makes Stage::isReady() a const method. No functional change. llvm-svn: 332443
* [llvm-mca] Introduce a pipeline Stage class and FetchStage.Matt Davis2018-05-1510-39/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is just an idea, really two ideas. I expect some push-back, but I realize that posting a diff is the most comprehensive way to express these concepts. This patch introduces a Stage class which represents the various stages of an instruction pipeline. As a start, I have created a simple FetchStage that is based on existing logic for how MCA produces instructions, but now encapsulated in a Stage. The idea should become more concrete once we introduce additional stages. The idea being, that when a stage completes, the next stage in the pipeline will be executed. Stages are chained together as a singly linked list to closely model a real pipeline. For now there is only one stage, so the stage-to-stage flow of instructions isn't immediately obvious. Eventually, Stage will also handle event notifications, but that functionality is not complete, and not destined for this patch. Ideally, an interested party can register for notifications from a particular stage. Callbacks will be issued to these listeners at various points in the execution of the stage. For now, eventing functionality remains similar to what it has been in mca::Backend. We will be building-up the Stage class as we move on, such as adding debug output. This patch also removes the unique_ptr<Instruction> return value from InstrBuilder::createInstruction. An Instruction pointer is still produced, but now it's up to the caller to decide how that item should be managed post-allocation (e.g., smart pointer). This allows the Fetch stage to create instructions and manage the lifetime of those instructions as it wishes, and not have to be bound to any specific managed pointer type. Other callers of createInstruction might have different requirements, and thus can manage the pointer to fit their needs. Another idea would be to push the ownership to the RCU. Currently, the FetchStage will wrap the Instruction pointer in a shared_ptr. This allows us to remove the Instruction container in Backend, which was probably going to disappear, or move, at some point anyways. Note that I did run these changes through valgrind, to make sure we are not leaking memory. While the shared_ptr comes with some additional overhead it relieves us from having to manage a list of generated instructions, and/or make lookup calls to remove the instructions. I realize that both the Stage class and the Instruction pointer management (mentioned directly above) are separate but related ideas, and probably should land as separate patches; I am happy to do that if either idea is decent. The main reason these two ideas are together is that Stage::execute() can mutate an InstRef. For the fetch stage, the InstRef is populated as the primary action of that stage (execute()). I didn't want to change the Stage interface to support the idea of generating an instruction. Ideally, instructions are to be pushed through the pipeline. I didn't want to draw too much of a specialization just for the fetch stage. Excuse the word-salad. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: llvm-commits, mgorny, javed.absar, tschuett, gbedwell Differential Revision: https://reviews.llvm.org/D46741 llvm-svn: 332390
* [llvm-mca] use a formatted_raw_ostream to insert padding and get rid of ↵Andrea Di Biagio2018-05-153-92/+76
| | | | | | tabs. NFC llvm-svn: 332381
* [llvm-mca] Strip leading tabs and spaces from instruction strings before ↵Andrea Di Biagio2018-05-153-11/+54
| | | | | | printing. NFC llvm-svn: 332361
* [llvm-mca] Remove unused include header files. NFCAndrea Di Biagio2018-05-151-4/+3
| | | | | | Also, run clang-format on RetireControlUnit.cpp. llvm-svn: 332337
* [llvm-mca] Add file header to RetireControlUnit.cpp.Andrea Di Biagio2018-05-151-0/+15
| | | | | | | Strictly speaking, this is not necessary for .cpp files. However, other .cpp files from this same tool have it. This also matches what we do in other tools. llvm-svn: 332334
* [llvm-mca] Improved support for dependency-breaking instructions.Andrea Di Biagio2018-05-144-35/+54
| | | | | | | | | The tool assumes that a zero-latency instruction that doesn't consume hardware resources is an optimizable dependency-breaking instruction. That means, it doesn't have to wait on register input operands, and it doesn't consume any physical register. The PRF knows how to optimize it at register renaming stage. llvm-svn: 332249
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-145-37/+41
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* Move standard library inclusions to after internal inclusions.David Blaikie2018-05-111-3/+3
| | | | llvm-svn: 332124
* llvm-mca: Add missing includesDavid Blaikie2018-05-092-1/+5
| | | | | | | Move the header include in the primary source file to the top to validate that it doesn't depend on any other inclusions. llvm-svn: 331897
* [llvm-mca] Avoid exposing index values in the MCA interfaces.Matt Davis2018-05-0716-173/+204
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch eliminates many places where we originally needed to pass index values to represent an instruction. The index is still used as a key, in various parts of MCA. I'm not comfortable eliminating the index just yet. By burying the index in the instruction, we can avoid exposing that value in many places. Eventually, we should consider removing the Instructions list in the Backend all together, it's only used to hold and reclaim the memory for the allocated Instruction instances. Instead we could pass around a smart pointer. But that's a separate discussion/patch. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46367 llvm-svn: 331660
* [llvm-mca] removes flag -instruction-tables from the "View Options" category.Andrea Di Biagio2018-05-051-25/+15
| | | | | | | | This patch also improves the description of a couple of flags in the view options. With this change, the -help now specifies which views are enabled by default. llvm-svn: 331594
* [llvm-mca] minor tweak to the resource pressure printing functionality. NFC.Andrea Di Biagio2018-05-051-1/+1
| | | | llvm-svn: 331590
* [llvm-mca] Add descriptive names for the TimelineView report characters. NFC.Matt Davis2018-05-042-8/+18
| | | | | | | | | | | | | | | | Summary: This change makes the TimelineView source simpler to read and easier to modify in the future. This patch introduces a class of static chars used as the display values in the TimelineView report, this change just eliminates a few magic characters. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46409 llvm-svn: 331540
* [llvm-mca] use colors for warnings and notes generated by InstrBuilder.Andrea Di Biagio2018-05-042-10/+10
| | | | llvm-svn: 331517
* [llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.Andrea Di Biagio2018-05-044-11/+13
| | | | | | | | | We don't need to pass the instruction index to the method that constructs new instruction descriptors. No functional change intended. llvm-svn: 331516
* [llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch ↵Matt Davis2018-05-015-132/+175
| | | | | | | | | | translation unit into its own translation unit. NFC The logic remains the same. Eventually, I see the RCU acting as its own separate stage in the instruction pipeline. Differential Revision: https://reviews.llvm.org/D46331 llvm-svn: 331316
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-0111-20/+20
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.Andrea Di Biagio2018-04-302-2/+4
| | | | | | | | | | | | | | | | This fixes PR37293. We can have scheduling classes with no write latency entries, that still consume processor resources. We don't want to treat those instructions as zero-latency instructions; they still have to be issued to the underlying pipelines, so they still consume resource cycles. This is likely to be a regression which I have accidentally introduced at revision 330807. Now, if an instruction has a non-empty set of write processor resources, we conservatively treat it as a normal (i.e. non zero-latency) instruction. llvm-svn: 331193
* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-301-1/+1
| | | | | | | | | Added Intel Atom tests to verify that the tool correctly generates instruction tables even if the CPU is in-order. Fixes PR37282. llvm-svn: 331169
* [MCA] [NFC] Remove unused Index formal from ResourceManager::issueInstructionMatt Davis2018-04-262-3/+3
| | | | | | | | | | | | | | Summary: The instruction index was never referenced in the body. Just a minor cleanup. Reviewers: andreadb Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46142 llvm-svn: 331001
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