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* [llvm-mca] Initialize each element in vector TimelineView::UsedBuffers to a ↵Andrea Di Biagio2018-08-282-14/+18
| | | | | | | | | default invalid buffer descriptor. NFCI Also change the default buffer size for UsedBuffer entries to -1 (i.e. "unknown size"). No functional change intended. llvm-svn: 340830
* [llvm-mca][TimelineView] Force the same number of executions for every entry ↵Andrea Di Biagio2018-08-282-70/+106
| | | | | | | | | | | | | | | | | | | in the 'wait-times' table. This patch also uses colors to highlight problematic wait-time entries. A problematic entry is an entry with an high wait time that tends to match (or exceed) the size of the scheduler's buffer. Color RED is used if an instruction had to wait an average number of cycles which is bigger than (or equal to) the size of the underlying scheduler's buffer. Color YELLOW is used if the time (in cycles) spend waiting for the operands or pipeline resources is bigger than half the size of the underlying scheduler's buffer. Color MAGENTA is used if an instruction does not consume buffer resources according to the scheduling model. llvm-svn: 340825
* [llvm-mca] Pass an instruction reference when notifying event listeners ↵Andrea Di Biagio2018-08-285-32/+30
| | | | | | about reserved/released buffer resources. NFC llvm-svn: 340821
* [llvm-mca] Remove unused include. NFCAndrea Di Biagio2018-08-271-1/+0
| | | | llvm-svn: 340768
* [llvm-mca] Introduce the llvm-mca library and organize the directory ↵Matt Davis2018-08-2741-62/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accordingly. NFC. Summary: This patch introduces llvm-mca as a library. The driver (llvm-mca.cpp), views, and stats, are not part of the library. Those are separate components that are not required for the functioning of llvm-mca. The directory has been organized as follows: All library source files now reside in: - `lib/HardwareUnits/` - All subclasses of HardwareUnit (these represent the simulated hardware components of a backend). (LSUnit does not inherit from HardwareUnit, but Scheduler does which uses LSUnit). - `lib/Stages/` - All subclasses of the pipeline stages. - `lib/` - This is the root of the library and contains library code that does not fit into the Stages or HardwareUnit subdirs. All library header files now reside in the `include` directory and mimic the same layout as the `lib` directory mentioned above. In the (near) future we would like to move the library (include and lib) contents from tools and into the core of llvm somewhere. That change would allow various analysis and optimization passes to make use of MCA functionality for things like cost modeling. I left all of the non-library code just where it has always been, in the root of the llvm-mca directory. The include directives for the non-library source file have been updated to refer to the llvm-mca library headers. I updated the llvm-mca/CMakeLists.txt file to include the library headers, but I made the non-library code explicitly reference the library's 'include' directory. Once we eventually (hopefully) migrate the MCA library components into llvm the include directives used by the non-library source files will be updated to point to the proper location in llvm. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D50929 llvm-svn: 340755
* [llvm-mca] Remove unused method. NFC.Matt Davis2018-08-271-1/+0
| | | | llvm-svn: 340754
* [llvm-mca] Improved report generated by the SchedulerStatistics view.Andrea Di Biagio2018-08-272-67/+99
| | | | | | | | | | | | | Before this patch, the SchedulerStatistics only printed the maximum number of buffer entries consumed in each scheduler's queue at a given point of the simulation. This patch restructures the reported table, and adds an extra field named "Average number of used buffer entries" to it. This patch also uses different colors to help identifying bottlenecks caused by high scheduler's buffer pressure. llvm-svn: 340746
* [llvm-mca] Move ResourceManager from Scheduler into its own file. NFC.Matt Davis2018-08-245-621/+672
| | | | | | This time I should be preserving history of the ResourceManager changes. llvm-svn: 340668
* [llvm-mca] Revert r340659. NFC.Matt Davis2018-08-245-672/+621
| | | | | | | | Choosing to revert the change and do it again, hopefully preserving the history of the changes by using svn copy instead of simply creating a new file from the contents within Scheduler. llvm-svn: 340661
* [llvm-mca] Move the ResourceManger from the Scheduler into its own file. NFC.Matt Davis2018-08-245-621/+672
| | | | llvm-svn: 340659
* [llvm-mca] Move views and stats into a Views subdir. NFC.Matt Davis2018-08-2423-38/+37
| | | | llvm-svn: 340645
* [llvm-mca] Fix parameter name. NFC.Walter Lee2018-08-231-2/+2
| | | | llvm-svn: 340570
* [llvm-mca] Set the Selection strategy to Default if nullptr is passed.Matt Davis2018-08-232-7/+20
| | | | | | * Set (not reset) the strategy in Scheduler::setCustomStrategyImpl() llvm-svn: 340566
* [llvm-mca] Fix wrong call to setCustomStrategy().Andrea Di Biagio2018-08-232-9/+9
| | | | | | | | | Thanks to @waltl for reporting this issue. I have also added an assert to check for invalid null strategy objects, and I have reworded a couple of code comments in Scheduler.h llvm-svn: 340545
* [llvm-mca] Allow the definition of custom strategies for selecting processor ↵Andrea Di Biagio2018-08-232-124/+182
| | | | | | | | | | | | | | | | | | | | | | | | | resource units. With this patch, users can now customize the pipeline selection strategy for scheduler resources. The resource selection strategy can be defined at processor resource granularity. This enables the definition of different strategies for different hardware schedulers. To override the strategy associated with a processor resource, users can call method ResourceManager::setCustomStrategy(), and pass a 'ResourceStrategy' object in input. Class ResourceStrategy is an abstract class which declares virtual method `ResourceStrategy::select()`. Method select() is meant to implement the actual strategy; it is responsible for picking the next best resource from a set of available pipeline resources. Custom strategy must simply override that method. By default, processor resources are associated with instances of 'DefaultResourceStrategy'. A 'DefaultResourceStrategy' internally implements a simple round-robin selector. For more details, please refer to the code comments in Scheduler.h. llvm-svn: 340536
* [llvm-mca] Clean up a comment about the Context class. NFC.Matt Davis2018-08-222-2/+2
| | | | llvm-svn: 340431
* [llvm-mca] Remove unused decl. NFC.Matt Davis2018-08-221-2/+0
| | | | llvm-svn: 340422
* [llvm-mca] Improved code comments and moved some method definitions from ↵Andrea Di Biagio2018-08-222-81/+98
| | | | | | Scheduler.h to Scheduler.cpp. NFC llvm-svn: 340395
* [llvm-mca] Remove unused decl. NFC.Matt Davis2018-08-211-1/+0
| | | | llvm-svn: 340316
* [llvm-mca] Add the ability to customize the instruction selection strategy ↵Andrea Di Biagio2018-08-212-34/+64
| | | | | | | | | | | | | | | | | | | | | | in the Scheduler. The constructor of Scheduler now accepts a SchedulerStrategy object, which is used internally by method Scheduler::select() to drive the instruction selection process. The goal of this patch is to enable the definition of custom selection strategies while reusing the same algorithms implemented by class Scheduler. The motivation is that, on some targets, the default strategy may not well approximate the selection logic in the hardware schedulers. This patch also adds the ability to pass a ResourceManager object to the constructor of Scheduler. This gives a bit more flexibility to the design, and potentially it allows to expose processor resources to SchedulerStrategy objects. Differential Revision: https://reviews.llvm.org/D51051 llvm-svn: 340314
* [llvm-mca] Replace use of llvm::any_of with std::any_of.Andrea Di Biagio2018-08-211-2/+3
| | | | | | This should unbreak the buildbots. llvm-svn: 340274
* [llvm-mca] Add method cycleEvent() to class Scheduler. NFCIAndrea Di Biagio2018-08-216-110/+123
| | | | | | | | | | | | | | | | | | | | The goal of this patch is to simplify the Scheduler's interface in preparation for D50929. Some methods in the Scheduler's interface should not be exposed to external users, since their presence makes it hard to both understand, and extend the Scheduler's interface. This patch removes the following two methods from the public Scheduler's API: - reclaimSimulatedResources() - updatePendingQueue() Their logic has been migrated to a new method named 'cycleEvent()'. Methods 'updateIssuedSet()' and 'promoteToReadySet()' still exist. However, they are now private members of class Scheduler. This simplifies the interaction with the Scheduler from the ExecuteStage. llvm-svn: 340273
* [llvm-mca] Remove unused formal parameter. NFC.Matt Davis2018-08-201-4/+4
| | | | llvm-svn: 340227
* [llvm-mca] Make the LSUnit a HardwareUnit, and allow derived classes to ↵Andrea Di Biagio2018-08-206-143/+153
| | | | | | | | | | | | | implement a different memory consistency model. The LSUnit is now a HardwareUnit, and it is owned by the mca::Context. Derived classes can now implement a different consistency model by overriding method `LSUnit::isReady()`. This patch also slightly refactors the Scheduler interface in the attempt to simplifying the interaction between ExecuteStage and the underlying Scheduler. llvm-svn: 340176
* [llvm-mca] Reformat a few lines (fix spacing). NFC.Matt Davis2018-08-173-7/+5
| | | | llvm-svn: 340065
* [llvm-mca] Removed references to HWStallEvent in Scheduler.h. NFCIAndrea Di Biagio2018-08-173-23/+47
| | | | | | | | | | class Scheduler should not know anything of hardware event listeners and hardware stall events (HWStallEvent). HWStallEvent objects should only be constructed by pipeline stages to notify listeners of hardware events. No functional change intended. llvm-svn: 340036
* [llvm-mca] Fix -Wpessimizing-move warnings introduced by r339923.Andrea Di Biagio2018-08-163-4/+4
| | | | | | Reported by buildbot `clang-with-lto-ubuntu` ( build #9858 ). llvm-svn: 339928
* [llvm-mca] Refactor how execution is orchestrated by the Pipeline.Andrea Di Biagio2018-08-1614-149/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes how instruction execution is orchestrated by the Pipeline. In particular, this patch makes it more explicit how instructions transition through the various pipeline stages during execution. The main goal is to simplify both the stage API and the Pipeline execution. At the same time, this patch fixes some design issues which are currently latent, but that are likely to cause problems in future if people start defining custom pipelines. The new design assumes that each pipeline stage knows the "next-in-sequence". The Stage API has gained three new methods: - isAvailable(IR) - checkNextStage(IR) - moveToTheNextStage(IR). An instruction IR can be executed by a Stage if method `Stage::isAvailable(IR)` returns true. Instructions can move to next stages using method moveToTheNextStage(IR). An instruction cannot be moved to the next stage if method checkNextStage(IR) (called on the current stage) returns false. Stages are now responsible for moving instructions to the next stage in sequence if necessary. Instructions are allowed to transition through multiple stages during a single cycle (as long as stages are available, and as long as all the calls to `checkNextStage(IR)` returns true). Methods `Stage::preExecute()` and `Stage::postExecute()` have now become redundant, and those are removed by this patch. Method Pipeline::runCycle() is now simpler, and it correctly visits stages on every begin/end of cycle. Other changes: - DispatchStage no longer requires a reference to the Scheduler. - ExecuteStage no longer needs to directly interact with the RetireControlUnit. Instead, executed instructions are now directly moved to the next stage (i.e. the retire stage). - RetireStage gained an execute method. This allowed us to remove the dependency with the RCU in ExecuteStage. - FecthStage now updates the "program counter" during cycleBegin() (i.e. before we start executing new instructions). - We no longer need Stage::Status to be returned by method execute(). It has been dropped in favor of a more lightweight llvm::Error. Overally, I measured a ~11% performance gain w.r.t. the previous design. I also think that the Stage interface is probably easier to read now. That being said, code comments have to be improved, and I plan to do it in a follow-up patch. Differential revision: https://reviews.llvm.org/D50849 llvm-svn: 339923
* [llvm-mca] Small refactoring in preparation for another patch that will ↵Andrea Di Biagio2018-08-1612-45/+67
| | | | | | | | | | | | improve the modularity of the Pipeline. NFCI The main difference is that now `cycleStart()` and `cycleEnd()` return an llvm::Error. This patch implements a few minor style changes, and adds missing 'const' to some methods. llvm-svn: 339885
* [llvm-mca] Minor style changes. NFCAndrea Di Biagio2018-08-154-27/+28
| | | | llvm-svn: 339823
* [llvm-mca] Fix PR38575: Avoid an invalid implicit truncation of a processor ↵Andrea Di Biagio2018-08-151-1/+1
| | | | | | | | | | | | | | | | | resource mask (an uint64_t value) to unsigned. This patch fixes a regression introduced at revision 338702. A processor resource mask was incorrectly implicitly truncated to an unsigned quantity. Later on, the truncated mask was used to initialize an element of a vector of processor resource descriptors. On targets with more than 32 processor resources, some elements of the vector are left uninitialized. As a consequence, this bug might have eventually caused a crash due to null dereference in the Scheduler. This patch fixes PR38575, and adds a test for it. llvm-svn: 339768
* [llvm-mca] Propagate fatal llvm-mca errors from library classes to driver.Matt Davis2018-08-1317-70/+131
| | | | | | | | | | | | | | | | | Summary: This patch introduces error handling to propagate the errors from llvm-mca library classes (or what will become library classes) up to the driver. This patch also introduces an enum to make clearer the intention of the return value for Stage::execute. This supports PR38101. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: llvm-commits, tschuett, gbedwell Differential Revision: https://reviews.llvm.org/D50561 llvm-svn: 339594
* [llvm-mca] Make InstrBuilder::getOrCreateInstrDesc private. NFC.Matt Davis2018-08-101-1/+2
| | | | llvm-svn: 339468
* [ADT] Normalize empty triple componentsPetr Hosek2018-08-081-1/+0
| | | | | | | | | | | | | | | | | LLVM triple normalization is handling "unknown" and empty components differently; for example given "x86_64-unknown-linux-gnu" and "x86_64-linux-gnu" which should be equivalent, triple normalization returns "x86_64-unknown-linux-gnu" and "x86_64--linux-gnu". autoconf's config.sub returns "x86_64-unknown-linux-gnu" for both "x86_64-linux-gnu" and "x86_64-unknown-linux-gnu". This changes the triple normalization to behave the same way, replacing empty triple components with "unknown". This addresses PR37129. Differential Revision: https://reviews.llvm.org/D50219 llvm-svn: 339294
* [llvm-mca] Speed up the computation of the wait/ready/issued sets in the ↵Andrea Di Biagio2018-08-034-100/+114
| | | | | | | | | | | | | | Scheduler. This patch is a follow-up to r338702. We don't need to use a map to model the wait/ready/issued sets. It is much more efficient to use a vector instead. This patch gives us an average 7.5% speedup (on top of the ~12% speedup obtained after r338702). llvm-svn: 338883
* [llvm-mca] Use a vector to store ResourceState objects in the ResourceManager.Andrea Di Biagio2018-08-022-81/+70
| | | | | | | | | | | | | | | We don't need to use a map to store ResourceState objects. The number of processor resources is known statically from the scheduling model. We can therefore use a vector, and reserve a slot for each processor resource that we want to simulate. Every time the ResourceManager queries the ResourceState vector, the index to the vector of ResourceState objects can be easily computed from the processor resource mask. This drastically reduces the time complexity of method ResourceManager::use() and method ResourceManager::release(). This patch gives an average speedup of 12%. llvm-svn: 338702
* [llvm-mca] Correctly update the rank in `Scheduler::select()`.Andrea Di Biagio2018-08-011-1/+3
| | | | | | Found by inspection. llvm-svn: 338579
* [llvm-mca] Improve code comments. NFC.Andrea Di Biagio2018-08-012-2/+2
| | | | llvm-svn: 338513
* [llvm-mca] Update the help text to reflect "physical" registers. NFC.Matt Davis2018-07-311-1/+1
| | | | llvm-svn: 338430
* [llvm-mca] Remove README.txtAndrea Di Biagio2018-07-311-865/+0
| | | | | | | | | | | | | | | | A detailed description of the tool has been recently added by Matt to CommandGuide/llvm-mca.rst. File README.txt is now redundant and can be removed; all the relevant user-guide information has been improved and then moved to llvm-mca.rst. In future, we should add another .rst for the "llvm-mca developer manual" to provide infromation about: - llvm-mca internals. - How to add custom stages to the simulated pipeline. - How to provide extra processor info in the scheduling model to improve the analysis performed by llvm-mca. llvm-svn: 338386
* [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.Andrea Di Biagio2018-07-314-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches llvm-mca how to identify dependency breaking instructions on btver2. An example of dependency breaking instructions is the zero-idiom XOR (example: `XOR %eax, %eax`), which always generates zero regardless of the actual value of the input register operands. Dependency breaking instructions don't have to wait on their input register operands before executing. This is because the computation is not dependent on the inputs. Not all dependency breaking idioms are also zero-latency instructions. For example, `CMPEQ %xmm1, %xmm1` is independent on the value of XMM1, and it generates a vector of all-ones. That instruction is not eliminated at register renaming stage, and its opcode is issued to a pipeline for execution. So, the latency is not zero. This patch adds a new method named isDependencyBreaking() to the MCInstrAnalysis interface. That method takes as input an instruction (i.e. MCInst) and a MCSubtargetInfo. The default implementation of isDependencyBreaking() conservatively returns false for all instructions. Targets may override the default behavior for specific CPUs, and return a value which better matches the subtarget behavior. In future, we should teach to Tablegen how to automatically generate the body of isDependencyBreaking from scheduling predicate definitions. This would allow us to expose the knowledge about dependency breaking instructions to the machine schedulers (and, potentially, other codegen passes). Differential Revision: https://reviews.llvm.org/D49310 llvm-svn: 338372
* [MCA] Avoid an InstrDesc copy in mca::LSUnit::reserve.Dean Michael Berris2018-07-261-1/+1
| | | | | | | | | | | | | | | | | | Summary: InstrDesc contains 4 vectors (as well as some other data), so it's expensive to copy. Authored By: orodley Reviewers: andreadb, mattd, dberris Reviewed By: mattd, dberris Subscribers: dberris, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49775 llvm-svn: 337985
* [llvm-mca][BtVer2] teach how to identify false dependencies on partially writtenAndrea Di Biagio2018-07-154-58/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers. The goal of this patch is to improve the throughput analysis in llvm-mca for the case where instructions perform partial register writes. On x86, partial register writes are quite difficult to model, mainly because different processors tend to implement different register merging schemes in hardware. When the code contains partial register writes, the IPC (instructions per cycles) estimated by llvm-mca tends to diverge quite significantly from the observed IPC (using perf). Modern AMD processors (at least, from Bulldozer onwards) don't rename partial registers. Quoting Agner Fog's microarchitecture.pdf: " The processor always keeps the different parts of an integer register together. For example, AL and AH are not treated as independent by the out-of-order execution mechanism. An instruction that writes to part of a register will therefore have a false dependence on any previous write to the same register or any part of it." This patch is a first important step towards improving the analysis of partial register updates. It changes the semantic of RegisterFile descriptors in tablegen, and teaches llvm-mca how to identify false dependences in the presence of partial register writes (for more details: see the new code comments in include/Target/TargetSchedule.h - class RegisterFile). This patch doesn't address the case where a write to a part of a register is followed by a read from the whole register. On Intel chips, high8 registers (AH/BH/CH/DH)) can be stored in separate physical registers. However, a later (dirty) read of the full register (example: AX/EAX) triggers a merge uOp, which adds extra latency (and potentially affects the pipe usage). This is a very interesting article on the subject with a very informative answer from Peter Cordes: https://stackoverflow.com/questions/45660139/how-exactly-do-partial-registers-on-haswell-skylake-perform-writing-al-seems-to In future, the definition of RegisterFile can be extended with extra information that may be used to identify delays caused by merge opcodes triggered by a dirty read of a partial write. Differential Revision: https://reviews.llvm.org/D49196 llvm-svn: 337123
* [llvm-mca] Turn InstructionTables into a Stage.Matt Davis2018-07-144-77/+61
| | | | | | | | | | | | | | | | | Summary: This patch converts the InstructionTables class into a subclass of mca::Stage. This change allows us to use the Stage's inherited Listeners for event notifications. This also allows us to create a simple pipeline for viewing the InstructionTables report. I have been working on a follow on patch that should cleanup addView in InstructionTables. Right now, addView adds the view to both the Listener list and Views list. The follow-on patch addresses the fact that we don't really need two lists in this case. That change is not specific to just InstructionTables, so it will be a separate patch. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49329 llvm-svn: 337113
* [llvm-mca] Remove unused InstRef formal from pre and post execute callbacks. ↵Matt Davis2018-07-145-12/+12
| | | | | | NFC. llvm-svn: 337077
* [llvm-mca] Improve a few debug prints. NFCAndrea Di Biagio2018-07-136-22/+24
| | | | llvm-svn: 337003
* [llvm-mca] Simplify the Pipeline constructor. NFCAndrea Di Biagio2018-07-132-7/+2
| | | | llvm-svn: 336984
* [llvm-mca] Removed unused arguments from methods in class Pipeline. NFCAndrea Di Biagio2018-07-132-14/+15
| | | | llvm-svn: 336983
* [llvm-mca] Constify SourceMgr::hasNext. NFC.Matt Davis2018-07-121-1/+1
| | | | llvm-svn: 336961
* [llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage.Matt Davis2018-07-1211-13/+40
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch clears up some of the semantics within the Stage class. Now, preExecute can be called multiple times per simulated cycle. Previously preExecute was only called once per cycle, and postExecute could have been called multiple times. Now, cycleStart/cycleEnd are called only once per simulated cycle. preExecute/postExecute can be called multiple times per cycle. This occurs because multiple execution events can occur during a single cycle. When stages are executed (Pipeline::runCycle), the postExecute hook will be called only if all Stages return a success from their 'execute' callback. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb Subscribers: tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D49250 llvm-svn: 336959
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