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* [llvm-mca] pass the correct set of used registers in checkRAT.Andrea Di Biagio2018-03-271-3/+5
| | | | | | | | | We were incorrectly initializing the array of used registers in method checkRAT. As a consequence, the number of register file stalls was misreported. Added a test to cover this case. llvm-svn: 328629
* [llvm-mca] Fix how views are added to the InstructionTables.Andrea Di Biagio2018-03-263-14/+20
| | | | | | | This should fix the stack-use-after-scope reported by the asan buildbots after revision 328493. llvm-svn: 328499
* [llvm-mca] Add a flag -instruction-info to enable/disable the instruction ↵Andrea Di Biagio2018-03-261-4/+14
| | | | | | info view. llvm-svn: 328493
* [llvm-mca] Add flag -instruction-tables to print the theoretical resource ↵Andrea Di Biagio2018-03-265-1/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pressure distribution for instructions (PR36874) The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
* [llvm-mca] run clang-format on all files.Andrea Di Biagio2018-03-2419-30/+17
| | | | | | This also addresses Simon's review comment in D44839. llvm-svn: 328428
* [llvm-mca] Remove unused field in InstrBuilder. NFCAndrea Di Biagio2018-03-241-1/+0
| | | | llvm-svn: 328427
* [llvm-mca] Split the InstructionInfoView from the SummaryView.Andrea Di Biagio2018-03-236-106/+155
| | | | llvm-svn: 328358
* [llvm-mca] update the ResourcePressureView after r328335. NFC.Andrea Di Biagio2018-03-232-8/+8
| | | | | | This should have been part of r328335. I forgot to svn add these files. llvm-svn: 328340
* [llvm-mca] Make the resource cost a double.Andrea Di Biagio2018-03-233-9/+10
| | | | | | | | This is done in preparation for the fix for PR36874. The number of cycles consumed for each pipe is now a double quantity. This allows reuse of the resource pressure view to print out instruction tables. llvm-svn: 328335
* [llvm-mca] Pass the InstrBuilder to the constructor of Backend.Andrea Di Biagio2018-03-233-8/+10
| | | | | | | This is done in preparation for the fix for PR36784. No functional change. llvm-svn: 328306
* [llvm-mca] Add flag -resource-pressure to enable/disable printing of the ↵Andrea Di Biagio2018-03-231-1/+7
| | | | | | | | | resource pressure view. By default, the tool always enables the resource pressure view. This flag lets user specify whether they want to add that view or not. llvm-svn: 328305
* [llvm-mca] Minor refactoring. NFCIAndrea Di Biagio2018-03-225-28/+31
| | | | | | Also, removed a couple of unused methods from class Instruction. llvm-svn: 328198
* [llvm-mca] Simplify (and better standardize) the Instruction interface.Andrea Di Biagio2018-03-226-31/+29
| | | | llvm-svn: 328190
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-03-2211-85/+69
| | | | llvm-svn: 328187
* [llvm-mca] Move the logic that computes the register file usage to the ↵Andrea Di Biagio2018-03-217-75/+103
| | | | | | | | | | | | | | | | | | | | | | | BackendStatistics view. With this patch, the "instruction dispatched" event now provides information related to the number of microarchitectural registers used in each register file. Similarly, the "instruction retired" event is now able to tell how may registers are freed in each register file. Currently, the BackendStatistics view is the only consumer of register usage/pressure information. BackendStatistics uses that info to print out a few general statistics (i.e. max number of mappings used; total mapping created). Before this patch, the BackendStatistics was forced to query the Backend to obtain the register pressure information. This helps removes that dependency. Now views are completely independent from the Backend. As a consequence, it should be easier to address PR36663 and further modularize the pipeline. Added a couple of test cases in the BtVer2 specific directory. llvm-svn: 328129
* [llvm-mca] Clean up some code. NFCAndrea Di Biagio2018-03-212-15/+4
| | | | | | Removed a couple of methods from DispatchUnit. llvm-svn: 328094
* [llvm-mca] add keyword override to a couple of methods in BackendStatistics.Andrea Di Biagio2018-03-201-2/+2
| | | | | | This should fix the buildbots after r328011. llvm-svn: 328029
* [llvm-mca] Remove const from a bunch of ArrayRef. NFCAndrea Di Biagio2018-03-206-14/+14
| | | | llvm-svn: 328018
* [llvm-mca] Move the logic that computes the scheduler's queue usage to the ↵Andrea Di Biagio2018-03-207-59/+119
| | | | | | | | | | | | | | | | | | | | | | BackendStatistics view. This patch introduces two new callbacks in the event listener interface to handle the "buffered resource reserved" event and the "buffered resource released" event. Every time a buffered resource is used, an event is generated. Before this patch, the Scheduler (with the help of the ResourceManager) was responsible for tracking the scheduler's queue usage. However, that design forced the Scheduler to 'publish' scheduler's queue pressure information through the Backend interface. The goal of this patch is to break the dependency between the BackendStatistics view, and the Backend. Now the Scheduler knows how to notify "buffer reserved/released" events. The scheduler's queue usage analysis has been moved to the BackendStatistics. Differential Revision: https://reviews.llvm.org/D44686 llvm-svn: 328011
* [llvm-mca] Use llvm::make_unique in a few places. NFCAndrea Di Biagio2018-03-204-23/+19
| | | | | | Also, clang-format a couple of DEBUG functions. llvm-svn: 327978
* [llvm-mca] Move the routine that computes processor resource masks to its ↵Andrea Di Biagio2018-03-209-89/+137
| | | | | | | | | | | | | | | | | | own file. Function computeProcResourceMasks is used by the ResourceManager (owned by the Scheduler) to compute resource masks for processor resources. Before this refactoring, there was an implicit dependency between the Scheduler and the InstrBuilder. That is because InstrBuilder has to know about resource masks when computing the set of processor resources consumed by a new instruction. With this patch, the functionality that computes resource masks has been extracted from the ResourceManager, and moved to a separate file (Support.h). This helps removing the dependency between the Scheduler and the InstrBuilder. No functional change intended. llvm-svn: 327973
* [llvm-mca] Remove unused method from ResourceManager. NFCAndrea Di Biagio2018-03-191-2/+0
| | | | llvm-svn: 327888
* [llvm-mca] Simplify code. NFCAndrea Di Biagio2018-03-193-48/+51
| | | | llvm-svn: 327886
* [llvm-mca] Add pipeline stall events.Andrea Di Biagio2018-03-197-118/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new class named HWStallEvent (see HWEventListener.h), and updates the event listener interface. A HWStallEvent represents a pipeline stall caused by the lack of hardware resources. Similarly to HWInstructionEvent, the event type is an unsigned, and the exact meaning depends on the subtarget. At the moment, HWStallEvent supports a few generic dispatch events. The main goals of this patch is to remove the logic that counts dispatch stalls from the DispatchUnit to the BackendStatistics view. Previously, DispatchUnit was responsible for counting and classifying dispatch stall events. With this patch, we delegate the task of counting and classifying stall events to the listeners (i.e. in our case, it is view "BackendStatistics"). So, the DispatchUnit doesn't have to do extra (unnecessary) bookkeeping. This patch also helps futher simplifying the Backend interface. Now class BackendStatistics no longer has to query the Backend interface to obtain the number of dispatch stalls. As a consequence, we can get rid of all the 'getNumXXX()' methods from class Backend. The long term goal is to remove all the remaining dependencies between the Backend and the BackendStatistics interface. Differential Revision: https://reviews.llvm.org/D44621 llvm-svn: 327837
* [llvm-mca] Allow the definition of multiple register files.Andrea Di Biagio2018-03-182-100/+249
| | | | | | | | | | | | | | | | | | | | This is a refactoring in preparation for other two changes that will allow scheduling models to define multiple register files. This is the first step towards fixing PR36662. class RegisterFile (in Dispatch.h) now can emulate multiple register files. Internally, it tracks the number of available physical registers in each register file (described by class RegisterFileInfo). Each register file is associated to a list of MCRegisterClass indices. Knowing the register class indices allows to map physical registers to register files. The long term goal is to allow processor models to optionally specify how many register files are implemented via tablegen. Differential Revision: https://reviews.llvm.org/D44488 llvm-svn: 327798
* [llvm-mca] Remove method getSchedModel() from the Backend.Andrea Di Biagio2018-03-163-7/+7
| | | | llvm-svn: 327756
* [llvm-mca] Remove unused methods from Backend. NFCAndrea Di Biagio2018-03-161-17/+0
| | | | llvm-svn: 327749
* [llvm-mca] Simplify code. NFC.Andrea Di Biagio2018-03-153-5/+7
| | | | | | | | Now both method DispatchUnit::checkRAT() and DispatchUnit::canDispatch take as input an Instruction refrence instead of an instruction descriptor. This was requested by Simon in D44488 to simplify the diff. llvm-svn: 327640
* [llvm-mca] Remove unused variable from InstrBuilder.cpp. NFCAndrea Di Biagio2018-03-141-1/+0
| | | | | | This was causing a buildbot failure. llvm-svn: 327517
* [llvm-mca] Move the logic that updates the register files from InstrBuilder ↵Andrea Di Biagio2018-03-146-58/+65
| | | | | | | | | | | | | | | | | | | to DispatchUnit. NFCI Before this patch, the register file was always updated at instruction creation time. That means, new read-after-write dependencies, and new temporary registers were allocated at instruction creation time. This patch refactors the code in InstrBuilder, and move all the logic that updates the register file into the dispatch unit. We only want to update the register file when instructions are effectively dispatched (not before). This refactoring also helps removing a bad dependency between the InstrBuilder and the DispatchUnit. No functional change intended. llvm-svn: 327514
* [llvm-mca] Remove the logic that computes the reciprocal throughput, and ↵Andrea Di Biagio2018-03-136-53/+39
| | | | | | | | | | | | | | | | | make the SummaryView independent from the Backend. NFCI Since r327420, the tool can query the MCSchedModel interface to obtain the reciprocal throughput information. As a consequence, method `ResourceManager::getRThroughput`, and method `Backend::getRThroughput` are no longer needed. This patch simplifies the code by removing the custom RThroughput computation. This patch also refactors class SummaryView by removing the dependency with the Backend object. No functional change intended. llvm-svn: 327425
* [llvm-mca] Simplify code that computes the latency of an instruction inAndrea Di Biagio2018-03-131-30/+5
| | | | | | | | | InstrBuilder. NFCI This was possible because of r327406, which added function`computeInstrLatency` to MCSchedModel. llvm-svn: 327415
* [llvm-mca] Use a const ArrayRef in a few places. NFCAndrea Di Biagio2018-03-132-15/+16
| | | | llvm-svn: 327396
* [llvm-mca] Fix unused variable warning in opt mode.Clement Courbet2018-03-131-1/+1
| | | | llvm-svn: 327394
* [llvm-mca] Refactor event listeners to make the backend agnostic to event types.Clement Courbet2018-03-1312-137/+162
| | | | | | | | | | Summary: This is a first step towards making the pipeline configurable. Subscribers: llvm-commits, andreadb Differential Revision: https://reviews.llvm.org/D44309 llvm-svn: 327389
* [llvm-mca] Fix use-of-uninitialized-value error reported by the MemorySanitizer.Andrea Di Biagio2018-03-101-1/+1
| | | | | | This should make the buildbots green again. llvm-svn: 327223
* [llvm-mca] BackendStatistics: early exit from method printSchedulerUsage if theAndrea Di Biagio2018-03-101-0/+9
| | | | | | no scheduler resources were consumed. llvm-svn: 327215
* [llvm-mca] Views are now independent from resource masks. NFCIAndrea Di Biagio2018-03-107-25/+25
| | | | | | | | | This change removes method Backend::getProcResourceMasks() and simplifies some logic in the Views. This effectively removes yet another dependency between the views and the Backend. No functional change intended. llvm-svn: 327214
* [llvm-mca] Move the logic that prints the summary into its own view. NFCIAndrea Di Biagio2018-03-096-91/+193
| | | | llvm-svn: 327128
* [llvm-mca] Run clang-format on the source code. NFCAndrea Di Biagio2018-03-096-24/+28
| | | | llvm-svn: 327125
* [llvm-mca] Fix handling of zero-latency instructions.Andrea Di Biagio2018-03-083-5/+2
| | | | | | | | | | | | | | | | | | | | This patch fixes a problem found when testing zero latency instructions on target AArch64 -mcpu=exynos-m3 / -mcpu=exynos-m1. On Exynos-m3/m1, direct branches are zero-latency instructions that don't consume any processor resources. The DispatchUnit marks zero-latency instructions as "executed", so that no scheduling is required. The event of instruction executed is then notified to all the listeners, and the reorder buffer (managed by the RetireControlUnit) is updated. In particular, the entry associated to the zero-latency instruction in the reorder buffer is marked as executed. Before this patch, the DispatchUnit forgot to assign a retire control unit token (RCUToken) to the zero-latency instruction. As a consequence, the RCUToken was used uninitialized. This was causing a crash in the RetireControlUnit logic. Fixes PR36650. llvm-svn: 327056
* [llvm-mca] add override keyword to method ResourcePressureView::printView().Andrea Di Biagio2018-03-081-1/+1
| | | | | | NFC. llvm-svn: 327027
* [llvm-mca] HWEventListener is a class, not struct.Andrea Di Biagio2018-03-082-2/+2
| | | | | | This should appease the buildbots. llvm-svn: 327025
* [llvm-mca] Unify the API for the various views. NFCIAndrea Di Biagio2018-03-0813-217/+280
| | | | | | | | | | | | | | | This allows the customization of the performance report. Users can specify their own custom sequence of views. Each view contributes a portion of the performance report generated by the BackendPrinter. Internally, class BackendPrinter keeps a sequence of views; views are printed out in sequence when method 'printReport()' is called. This patch addresses one of the two review comments from Clement in D43951. llvm-svn: 327018
* [llvm-mca] Emit the 'Instruction Info' table before the resource pressure view.Andrea Di Biagio2018-03-081-3/+3
| | | | | | | In future, both the summary information and the 'instruction info' table should be moved into a separate "Summary" view. llvm-svn: 327010
* [llvm-mca] LLVM Machine Code Analyzer.Andrea Di Biagio2018-03-0827-0/+5769
llvm-mca is an LLVM based performance analysis tool that can be used to statically measure the performance of code, and to help triage potential problems with target scheduling models. llvm-mca uses information which is already available in LLVM (e.g. scheduling models) to statically measure the performance of machine code in a specific cpu. Performance is measured in terms of throughput as well as processor resource consumption. The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM. The main goal of this tool is not just to predict the performance of the code when run on the target, but also help with diagnosing potential performance issues. Given an assembly code sequence, llvm-mca estimates the IPC (instructions per cycle), as well as hardware resources pressure. The analysis and reporting style were mostly inspired by the IACA tool from Intel. This patch is related to the RFC on llvm-dev visible at this link: http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html Differential Revision: https://reviews.llvm.org/D43951 llvm-svn: 326998
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