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* [llvm-mca] Pass the InstrBuilder to the constructor of Backend.Andrea Di Biagio2018-03-231-1/+1
| | | | | | | This is done in preparation for the fix for PR36784. No functional change. llvm-svn: 328306
* [llvm-mca] Simplify (and better standardize) the Instruction interface.Andrea Di Biagio2018-03-221-1/+1
| | | | llvm-svn: 328190
* [llvm-mca] Move the logic that computes the scheduler's queue usage to the ↵Andrea Di Biagio2018-03-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | BackendStatistics view. This patch introduces two new callbacks in the event listener interface to handle the "buffered resource reserved" event and the "buffered resource released" event. Every time a buffered resource is used, an event is generated. Before this patch, the Scheduler (with the help of the ResourceManager) was responsible for tracking the scheduler's queue usage. However, that design forced the Scheduler to 'publish' scheduler's queue pressure information through the Backend interface. The goal of this patch is to break the dependency between the BackendStatistics view, and the Backend. Now the Scheduler knows how to notify "buffer reserved/released" events. The scheduler's queue usage analysis has been moved to the BackendStatistics. Differential Revision: https://reviews.llvm.org/D44686 llvm-svn: 328011
* [llvm-mca] Use llvm::make_unique in a few places. NFCAndrea Di Biagio2018-03-201-3/+2
| | | | | | Also, clang-format a couple of DEBUG functions. llvm-svn: 327978
* [llvm-mca] Move the routine that computes processor resource masks to its ↵Andrea Di Biagio2018-03-201-1/+1
| | | | | | | | | | | | | | | | | | own file. Function computeProcResourceMasks is used by the ResourceManager (owned by the Scheduler) to compute resource masks for processor resources. Before this refactoring, there was an implicit dependency between the Scheduler and the InstrBuilder. That is because InstrBuilder has to know about resource masks when computing the set of processor resources consumed by a new instruction. With this patch, the functionality that computes resource masks has been extracted from the ResourceManager, and moved to a separate file (Support.h). This helps removing the dependency between the Scheduler and the InstrBuilder. No functional change intended. llvm-svn: 327973
* [llvm-mca] Add pipeline stall events.Andrea Di Biagio2018-03-191-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new class named HWStallEvent (see HWEventListener.h), and updates the event listener interface. A HWStallEvent represents a pipeline stall caused by the lack of hardware resources. Similarly to HWInstructionEvent, the event type is an unsigned, and the exact meaning depends on the subtarget. At the moment, HWStallEvent supports a few generic dispatch events. The main goals of this patch is to remove the logic that counts dispatch stalls from the DispatchUnit to the BackendStatistics view. Previously, DispatchUnit was responsible for counting and classifying dispatch stall events. With this patch, we delegate the task of counting and classifying stall events to the listeners (i.e. in our case, it is view "BackendStatistics"). So, the DispatchUnit doesn't have to do extra (unnecessary) bookkeeping. This patch also helps futher simplifying the Backend interface. Now class BackendStatistics no longer has to query the Backend interface to obtain the number of dispatch stalls. As a consequence, we can get rid of all the 'getNumXXX()' methods from class Backend. The long term goal is to remove all the remaining dependencies between the Backend and the BackendStatistics interface. Differential Revision: https://reviews.llvm.org/D44621 llvm-svn: 327837
* [llvm-mca] Simplify code. NFC.Andrea Di Biagio2018-03-151-1/+1
| | | | | | | | Now both method DispatchUnit::checkRAT() and DispatchUnit::canDispatch take as input an Instruction refrence instead of an instruction descriptor. This was requested by Simon in D44488 to simplify the diff. llvm-svn: 327640
* [llvm-mca] Move the logic that updates the register files from InstrBuilder ↵Andrea Di Biagio2018-03-141-18/+10
| | | | | | | | | | | | | | | | | | | to DispatchUnit. NFCI Before this patch, the register file was always updated at instruction creation time. That means, new read-after-write dependencies, and new temporary registers were allocated at instruction creation time. This patch refactors the code in InstrBuilder, and move all the logic that updates the register file into the dispatch unit. We only want to update the register file when instructions are effectively dispatched (not before). This refactoring also helps removing a bad dependency between the InstrBuilder and the DispatchUnit. No functional change intended. llvm-svn: 327514
* [llvm-mca] Refactor event listeners to make the backend agnostic to event types.Clement Courbet2018-03-131-43/+2
| | | | | | | | | | Summary: This is a first step towards making the pipeline configurable. Subscribers: llvm-commits, andreadb Differential Revision: https://reviews.llvm.org/D44309 llvm-svn: 327389
* [llvm-mca] Fix handling of zero-latency instructions.Andrea Di Biagio2018-03-081-5/+0
| | | | | | | | | | | | | | | | | | | | This patch fixes a problem found when testing zero latency instructions on target AArch64 -mcpu=exynos-m3 / -mcpu=exynos-m1. On Exynos-m3/m1, direct branches are zero-latency instructions that don't consume any processor resources. The DispatchUnit marks zero-latency instructions as "executed", so that no scheduling is required. The event of instruction executed is then notified to all the listeners, and the reorder buffer (managed by the RetireControlUnit) is updated. In particular, the entry associated to the zero-latency instruction in the reorder buffer is marked as executed. Before this patch, the DispatchUnit forgot to assign a retire control unit token (RCUToken) to the zero-latency instruction. As a consequence, the RCUToken was used uninitialized. This was causing a crash in the RetireControlUnit logic. Fixes PR36650. llvm-svn: 327056
* [llvm-mca] Unify the API for the various views. NFCIAndrea Di Biagio2018-03-081-5/+5
| | | | | | | | | | | | | | | This allows the customization of the performance report. Users can specify their own custom sequence of views. Each view contributes a portion of the performance report generated by the BackendPrinter. Internally, class BackendPrinter keeps a sequence of views; views are printed out in sequence when method 'printReport()' is called. This patch addresses one of the two review comments from Clement in D43951. llvm-svn: 327018
* [llvm-mca] LLVM Machine Code Analyzer.Andrea Di Biagio2018-03-081-0/+132
llvm-mca is an LLVM based performance analysis tool that can be used to statically measure the performance of code, and to help triage potential problems with target scheduling models. llvm-mca uses information which is already available in LLVM (e.g. scheduling models) to statically measure the performance of machine code in a specific cpu. Performance is measured in terms of throughput as well as processor resource consumption. The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM. The main goal of this tool is not just to predict the performance of the code when run on the target, but also help with diagnosing potential performance issues. Given an assembly code sequence, llvm-mca estimates the IPC (instructions per cycle), as well as hardware resources pressure. The analysis and reporting style were mostly inspired by the IACA tool from Intel. This patch is related to the RFC on llvm-dev visible at this link: http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html Differential Revision: https://reviews.llvm.org/D43951 llvm-svn: 326998
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