| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
to reflect the new license.
We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.
llvm-svn: 351636
|
| |
|
|
|
|
|
|
| |
compute ROB sizes."
This reverts accidental commit rL346394.
llvm-svn: 346398
|
| |
|
|
|
|
| |
sizes.
llvm-svn: 346394
|
| |
|
|
|
|
|
|
| |
MachineModuleInfo can only be used in code using lib/CodeGen, hence we
can keep a more specific reference to LLVMTargetMachine rather than just
TargetMachine around.
llvm-svn: 346182
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
This allows simplifying references of llvm::foo with foo when the needs
come in the future.
Reviewers: courbet, gchatelet
Reviewed By: gchatelet
Subscribers: javed.absar, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53455
llvm-svn: 344922
|
| |
|
|
| |
llvm-svn: 344907
|
| |
|
|
|
|
|
|
|
|
| |
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53429
llvm-svn: 344780
|
| |
|
|
|
|
|
|
|
|
| |
When fillMachineFunction generates a return on targets without a return opcode
(such as AArch64) it should pass an empty set of registers as the return
registers, not 0 which means register number zero.
Differential Revision: https://reviews.llvm.org/D53074
llvm-svn: 344139
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.
Reviewers: courbet, javed.absar
Subscribers: llvm-commits, tschuett, mgorny
Differential Revision: https://reviews.llvm.org/D52297
llvm-svn: 342644
|
| |
|
|
|
|
| |
rL342465 is breaking the MSVC buildbots.
llvm-svn: 342490
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
rL342465 is breaking the MSVC buildbots, but I need to revert this dependent revision as well.
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.
Reviewers: courbet, javed.absar
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D51856
llvm-svn: 342489
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
Added function to set a register to a particular value + tests.
Add EFLAGS test, use new setRegTo instead of setRegToConstant.
Reviewers: courbet, javed.absar
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D51856
llvm-svn: 342466
|
| |
|
|
| |
llvm-svn: 342465
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
And implement memory instructions on X86.
This fixes PR36906.
Reviewers: gchatelet
Reviewed By: gchatelet
Subscribers: lebedev.ri, filcab, mgorny, tschuett, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D48935
llvm-svn: 338567
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
subtarget features.
Summary: This fixes PR38008.
Reviewers: gchatelet, RKSimon
Subscribers: tschuett, craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D48820
llvm-svn: 336171
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
This allows targets to override code generation for some instructions.
As an example of override, this also moves ad-hoc instruction filtering
for X86 into the X86 ExegesisTarget.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48587
llvm-svn: 335582
|
| |
|
|
| |
llvm-svn: 335467
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
This ensures that the snippet always sees the same values for registers,
making measurements reproducible.
This will also allow exploring different values.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48542
llvm-svn: 335465
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Summary:
createX86FloatingPointStackifierPass is disabled until we handle
TracksLiveness correctly.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48360
llvm-svn: 335117
|
| |
|
|
|
|
|
|
|
|
| |
up to dwo output.
Part of PR37466.
Differential Revision: https://reviews.llvm.org/D47089
llvm-svn: 332881
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.
https://reviews.llvm.org/D46821
(with fixed ARM tests)
Authored by Guillaume Chatelet
llvm-svn: 332592
|
| |
|
|
|
|
| |
The revision failed to update the ARM tests.
llvm-svn: 332580
|
|
|
Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.
https://reviews.llvm.org/D46821
Authored by Guillaume Chatelet
llvm-svn: 332579
|