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* Revert r209235 as it broke two tests:Kevin Enderby2014-05-202-5/+5
| | | | | | | | Failing Tests (2): LLVM :: ExecutionEngine/MCJIT/stubs-sm-pic.ll LLVM :: ExecutionEngine/MCJIT/stubs.ll llvm-svn: 209236
* Update MachOObjectFile::getSymbolAddress so it returns UnknownAddressOrSizeKevin Enderby2014-05-202-5/+5
| | | | | | | for undefined symbols. Allowing llvm-nm to print spaces instead of 0’s for the value of undefined symbols in Mach-O files. llvm-svn: 209235
* [LSR] Canonicalize reg1 + ... + regN into reg1 + ... + 1*regN.Quentin Colombet2014-05-202-7/+10
| | | | | | | | | | | | | | This commit introduces a canonical representation for the formulae. Basically, as soon as a formula has more that one base register, the scaled register field is used for one of them. The register put into the scaled register is preferably a loop variant. The commit refactors how the formulae are built in order to produce such representation. This yields a more accurate, but still perfectible, cost model. <rdar://problem/16731508> llvm-svn: 209230
* PR19767: DebugInfo emission of pointer constants.David Blaikie2014-05-201-0/+51
| | | | | | | | | | | | | | | | | In refactoring DwarfUnit::isUnsignedDIType I restricted it to only work on values with signedness (unsigned or signed), asserting on anything else (which did uncover some bugs). But it turns out that we do need to emit constants of signless data, such as pointer constants - only null pointer constants are known to need this so far, but it's conceivable that there might be non-null pointer constants at some point (hardcoded address offsets for device drivers?). This patch just uses 'unsigned' for signless data such as pointer constants. Arguably we could use signless representations (DW_FORM_dataN) instead, allowing a trinary result from isUnsignedDIType (signed, unsigned, signless), but this seems reasonable for now. llvm-svn: 209223
* Avoids DCE on write_registerRenato Golin2014-05-201-0/+3
| | | | llvm-svn: 209222
* [PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16ImmediateAdam Nemet2014-05-201-0/+22
| | | | | | | | | | | | | The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64 backend. We matched an immediate offset with STWX8 even though it only supports register offset. The culprit is the complex-pattern predicate, SelectAddrIdx, which decides that if the offset is not ISD::Constant it must be a register. Many thanks to Bill Schmidt for testing this. llvm-svn: 209219
* Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes ↵Daniel Sanders2014-05-202-36/+36
| | | | | | | | | | | | and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
* [ARM64] Port basic-a64-diagnostics.s over to ARM64Bradley Smith2014-05-201-459/+529
| | | | llvm-svn: 209207
* Legalizer: Make bswap promotion safe for vectors.Benjamin Kramer2014-05-201-0/+17
| | | | llvm-svn: 209202
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-203-0/+219
| | | | llvm-svn: 209200
* TableGen: convert InstAlias's Emit bit to an int.Tim Northover2014-05-202-20/+12
| | | | | | | | | | | | | When multiple aliases overlap, the correct string to print can often be determined purely by considering the InstAlias declarations in some particular order. This allows the user to specify that order manually when desired, without resorting to hacking around with the default lexicographical order on Record instantiation, which is error-prone and ugly. I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4, uxtw". That's only true if Rn is the stack pointer. llvm-svn: 209199
* Teach isKnownNonNull that a nonnull return is not null. Add a test for this ↵Nick Lewycky2014-05-201-0/+17
| | | | | | case as well as the case of a nonnull attribute (already handled but not tested). llvm-svn: 209193
* DebugInfo: Emit function definitions within their namespace scope.David Blaikie2014-05-201-0/+44
| | | | | | | | This workaround (presumably for ancient GDB) doesn't appear to be required (GDB 7.5 seems to tolerate function definition DIEs in namespace scope just fine). llvm-svn: 209189
* Follow up to 209187, updating a test to use FileCheck. Needed to ignore an ↵David Blaikie2014-05-201-1/+2
| | | | | | extra DW_TAG_class_type llvm-svn: 209188
* Update test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll to use FileCheck.David Blaikie2014-05-201-2/+17
| | | | llvm-svn: 209187
* Add 'nonnull', a new parameter and return attribute which indicates that the ↵Nick Lewycky2014-05-201-0/+5
| | | | | | pointer is not null. Instcombine will elide comparisons between these and null. Patch by Luqman Aden! llvm-svn: 209185
* LTO: Add a testcase for linking modules with incompatible Debug InfoAdrian Prantl2014-05-192-0/+26
| | | | | | | Versions. rdar://problem/16926122 llvm-svn: 209183
* OK, NAKAMURA Takumi beat me to this change. So backing out my addition ofKevin Enderby2014-05-191-1/+0
| | | | | | llvm-size to the list so it only has one. Sorry for the noise. llvm-svn: 209181
* David Blaikie pointed out that the test added in r209158 fails in theKevin Enderby2014-05-191-0/+1
| | | | | | | check-llvm target under CMake. And the test/CMakeFiles.txt needs to have llvm-size added to the list. llvm-svn: 209179
* DebugInfo: Assume all subprogram DIEs have been created before any abstract ↵David Blaikie2014-05-192-2/+2
| | | | | | | | | | | | | | subprograms are constructed. Since we visit the whole list of subprograms for each CU at module start, this is clearly true - don't test for the case, just assert it. A few old test cases seemed to have incomplete subprogram lists, but any attempt to reproduce them shows full subprogram lists that even include entities that have been completely inlined and the out of line definition removed. llvm-svn: 209178
* [CMake] Add llvm-size to check-llvm, to fix build since r209158.NAKAMURA Takumi2014-05-191-0/+1
| | | | llvm-svn: 209177
* [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.Chad Rosier2014-05-191-0/+15
| | | | | | | Patch by Dave Estes<cestes@codeaurora.org>! PR19761 http://reviews.llvm.org/D3829 llvm-svn: 209176
* DebugInfo: Don't include DW_AT_inline on each abstract definition multiple ↵David Blaikie2014-05-191-0/+3
| | | | | | | | | | | | | | | | | times. When I refactored this in r208636 I accidentally caused this to be added multiple times to each abstract subprogram (not accounting for the deduplicating effect of the InlinedSubprogramDIEs set). This got better in r208798 when the abstract definitions got the attribute added to them at construction time, but still had the redundant copies introduced in r208636. This commit removes those excess DW_AT_inlines and relies solely on the insertion in r208798. llvm-svn: 209166
* DebugInfo: Fix missing inlined_subroutines caused by r208748.David Blaikie2014-05-191-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | The check in DwarfDebug::constructScopeDIE was meant to consider inlined subroutines as any non-top-level scope that was a subprogram. Instead of checking "not top level scope" it was checking if the /subprogram's/ scope was non-top-level. Fix this and beef up a test case to demonstrate some of the missing inlined_subroutines are no longer missing. In the course of fixing this I also found that r208748 (with this fix) found one /extra/ inlined_subroutine in concrete_out_of_line.ll due to two inlined_subroutines having the same inlinedAt location. The previous implementation was collapsing these into a single inlined subroutine. I'm not sure what the original code was that created this .ll file so I'm not sure if this actually happens in practice today. Since we deliberately include column information to disambiguate two calls on the same line, that may've addressed this bug in the frontend, but it's good to know that workaround isn't necessary for this particular case anymore. llvm-svn: 209165
* [ConstantHoisting][X86] Change the cost model to never hoist constants for ↵Juergen Ributzka2014-05-191-0/+9
| | | | | | | | | | | | | | | types larger than i128. Currently the X86 backend doesn't support types larger than i128 very well. For example an i192 multiply will assert in codegen when the 2nd argument is a constant and the constant got hoisted. This fix changes the cost model to never hoist constants for types larger than i128. Once the codegen issues have been resolved, the cost model can be updated to allow also larger types. This is related to <rdar://problem/16954938> llvm-svn: 209162
* [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.Andrea Di Biagio2014-05-191-0/+447
| | | | | | | | | | Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159
* Implement MachOObjectFile::isSectionData() and MachOObjectFile::isSectionBSSKevin Enderby2014-05-192-0/+15
| | | | | | | | so that llvm-size will total up all the sections in the Berkeley format. This allows for rough categorizations for Mach-O sections. And allows the total of llvm-size’s Berkeley and System V formats to be the same. llvm-svn: 209158
* Added more insertps optimizationsFilipe Cabecinhas2014-05-193-2/+221
| | | | | | | | | | | | | | | | | | | | Summary: When inserting an element that's coming from a vector load or a broadcast of a vector (or scalar) load, combine the load into the insertps instruction. Added PerformINSERTPSCombine for the case where we need to fix the load (load of a vector + insertps with a non-zero CountS). Added patterns for the broadcasts. Also added tests for SSE4.1, AVX, and AVX2. Reviewers: delena, nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3581 llvm-svn: 209156
* Fix testers by removing dubious testcase for r209154.Lang Hames2014-05-192-1/+0
| | | | | | | | It turns out that not all the world is x86-64. Who knew? I'll get to work on a more appropriate test case for this patch. llvm-svn: 209155
* [RuntimeDyld] Fix x86-64 MachO GOT relocation handling.Lang Hames2014-05-192-0/+1
| | | | | | | | | | | For GOT relocations the addend should modify the offset to the GOT entry, not the value of the entry itself. Teach RuntimeDyldMachO to do The Right Thing here. Fixes <rdar://problem/16961886>. llvm-svn: 209154
* Kill symbolization functionality in llvm-dwarfdump. We have llvm-symbolizer ↵Alexey Samsonov2014-05-196-97/+62
| | | | | | for that. llvm-svn: 209152
* Check the alwaysinline attribute on the call as well as on the caller.Peter Collingbourne2014-05-191-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D3815 llvm-svn: 209150
* reverting r209132Jyotsna Verma2014-05-192-582/+0
| | | | llvm-svn: 209139
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-191-2/+2
| | | | llvm-svn: 209134
* Hexagon: Add encoding bits to the mpy instructions.Jyotsna Verma2014-05-192-0/+582
| | | | llvm-svn: 209132
* [mips][mips64r6] Sorted *_ENC, *_DESC classes and testsZoran Jovanovic2014-05-192-36/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
* Flip on vectorization of bswap intrinsics.Benjamin Kramer2014-05-191-0/+44
| | | | | | | | | The cost model conservatively assumes that it will always get scalarized and that's about as good as we can get with the generic TTI; reasoning whether a shuffle with an efficient lowering is available is hard. We can override that conservative estimate for some targets in the future. llvm-svn: 209125
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-193-6/+133
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* Added inst-combine for 'MIN(MIN(A, 97), 23)' and 'MAX(MAX(A, 23), 97)'Dinesh Dwivedi2014-05-191-0/+52
| | | | | | | | | | | This removes TODO added in r208849 [http://reviews.llvm.org/D3629] MIN(MIN(A, 97), 23) -> MIN(A, 23) MAX(MAX(A, 23), 97) -> MAX(A, 97) Differential Revision: http://reviews.llvm.org/D3785 llvm-svn: 209110
* Change the blend tests to AVX, not AVX2.Filipe Cabecinhas2014-05-191-1/+1
| | | | llvm-svn: 209107
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-182-0/+60
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* Handle ConstantAggregateZero when upgrading global_ctors.Rafael Espindola2014-05-172-0/+3
| | | | llvm-svn: 209075
* Revert r209049 and r209065, "Add support for combining GEPs across PHI nodes"NAKAMURA Takumi2014-05-171-56/+0
| | | | | | It broke clang selfhosting even after r209065. llvm-svn: 209067
* test: fix copy-paste mistakeSaleem Abdulrasool2014-05-171-1/+1
| | | | | | Accidental over-quoting of the match string. llvm-svn: 209058
* ARM: use the proper target object format for WoASaleem Abdulrasool2014-05-171-0/+15
| | | | | | | | WoA uses COFF, not ELF. ARMISelLowering::createTLOF would previously return ELF for any non-MachO platform. This was a missed site when the original change for target format support for Windows on ARM was done. llvm-svn: 209057
* [x86] Fix a bad predicate I spotted by inspection -- pshufhw and pshuflwChandler Carruth2014-05-171-1/+1
| | | | | | | | | | were added in SSE2, no SSSE3. Found this while auditing all uses of SSSE3 in the X86 target. I don't actually expect this to make a significant difference on anything and I don't have any detailed test cases but I updated the existing test cases that already covered some of this code path. llvm-svn: 209056
* [DWARF parser] Teach DIContext to fetch short (non-linkage) function names ↵Alexey Samsonov2014-05-171-1/+7
| | | | | | | | | | for a given address. Change --functions option in llvm-symbolizer tool to accept values "none", "short" or "linkage". Update the tests and docs accordingly. llvm-svn: 209050
* Add support for combining GEPs across PHI nodesLouis Gerbarg2014-05-161-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently LLVM will generally merge GEPs. This allows backends to use more complex addressing modes. In some cases this is not happening because there is PHI inbetween the two GEPs: GEP1--\ |-->PHI1-->GEP3 GEP2--/ This patch checks to see if GEP1 and GEP2 are similiar enough that they can be cloned (GEP12) in GEP3's BB, allowing GEP->GEP merging (GEP123): GEP1--\ --\ --\ |-->PHI1-->GEP3 ==> |-->PHI2->GEP12->GEP3 == > |-->PHI2->GEP123 GEP2--/ --/ --/ This also breaks certain use chains that are preventing GEP->GEP merges that the the existing instcombine would merge otherwise. Tests included. rdar://15547484 llvm-svn: 209049
* Added tests for the cost of lowering VSELECT instructions.Filipe Cabecinhas2014-05-161-0/+126
| | | | llvm-svn: 209045
* Implemented special cases for PerformVSELECTCombine.Filipe Cabecinhas2014-05-161-5/+5
| | | | | | | | | | vselects with constant masks, after legalization, will get turned into specialized shuffle_vectors so they can be matched to blend+imm instructions. Fixed some tests. llvm-svn: 209044
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