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* Fix the root cause of PR15348 by correctly handling alignment 0 onChandler Carruth2013-02-252-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | memory intrinsics in the SDAG builder. When alignment is zero, the lang ref says that *no* alignment assumptions can be made. This is the exact opposite of the internal API contracts of the DAG where alignment 0 indicates that the alignment can be made to be anything desired. There is another, more explicit alignment that is better suited for the role of "no alignment at all": an alignment of 1. Map the intrinsic alignment to this early so that we don't end up generating aligned DAGs. It is really terrifying that we've never seen this before, but we suddenly started generating a large number of alignment 0 memcpys due to the new code to do memcpy-based copying of POD class members. That patch contains a bug that rounds bitfield alignments down when they are the first field. This can in turn produce zero alignments. This fixes weird crashes I've seen in library users of LLVM on 32-bit hosts, etc. llvm-svn: 176022
* CVP: If we have a PHI with an incoming select, try to skip the select.Benjamin Kramer2013-02-241-0/+20
| | | | | | | | | | This is a common pattern with dyn_cast and similar constructs, when the PHI no longer depends on the select it can often be turned into a simpler construct or even get hoisted out of the loop. PR15340. llvm-svn: 175995
* Fix invalid IR in test, missing incoming value for PHI node.Benjamin Kramer2013-02-241-1/+1
| | | | llvm-svn: 175994
* Revert r169638 because it broke Mesa llvmpipe tests.Nadav Rotem2013-02-242-2/+2
| | | | | | Fix PR15239. llvm-svn: 175985
* Some more tests for the global structure vectorizerRenato Golin2013-02-231-20/+596
| | | | llvm-svn: 175964
* X86: Disable cmov-memory patterns on subtargets without cmov.Benjamin Kramer2013-02-231-0/+11
| | | | | | Fixes PR15115. llvm-svn: 175962
* Expand pseudos/macros for Selt. This is the last of the complexReed Kotler2013-02-232-10/+11
| | | | | | macros.The rest is some small misc. stuff. llvm-svn: 175950
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-232-0/+69
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 llvm-svn: 175940
* Use getSplitDebugFilename when constructing the skeleton cu andEric Christopher2013-02-221-1/+1
| | | | | | update testcase accordingly to give the correct name to the cu. llvm-svn: 175934
* [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.Akira Hatanaka2013-02-222-14/+29
| | | | llvm-svn: 175920
* Fix test by matching movaps instead of AVX-only vmovapsPeter Collingbourne2013-02-221-2/+2
| | | | llvm-svn: 175914
* x86_64: designate most general purpose and SSE registers as callee save ↵Peter Collingbourne2013-02-221-0/+24
| | | | | | under coldcc llvm-svn: 175911
* Remove unused CHECK lines copied from another testPete Cooper2013-02-221-8/+0
| | | | llvm-svn: 175905
* More tests to global struct vectorizerRenato Golin2013-02-221-0/+146
| | | | llvm-svn: 175898
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-2227-407/+407
| | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] llvm-svn: 175884
* Use references to attribute groups on the call/invoke instructions.Bill Wendling2013-02-2239-149/+237
| | | | | | | Listing all of the attributes for the callee of a call/invoke instruction is way too much and makes the IR unreadable. Use references to attributes instead. llvm-svn: 175877
* Expand mips16 SelT form pseudso/macros.Reed Kotler2013-02-227-4/+85
| | | | llvm-svn: 175862
* Fix isa<> check which could never be true.Pete Cooper2013-02-221-0/+32
| | | | | | | | | | | | It was incorrectly checking a Function* being an IntrinsicInst* which isn't possible. It should always have been checking the CallInst* instead. Added test case for x86 which ensures we only get one constant load. It was 2 before this change. rdar://problem/13267920 llvm-svn: 175853
* Previously, parsing capability of the .debug_frame section was addedEli Bendersky2013-02-211-0/+13
| | | | | | | | | | | | | | | | to lib/DebugInfo, with dumping in llvm-dwarfdump. This patch adds initial ability to parse and dump CFA instructions contained in entries. To keep it manageable, the patch omits some more advanced capabilities (accounted in TODOs): * Parsing of instructions with BLOCK arguments (expression lists) * Dumping of actual instruction arguments (currently only names are dumped). This is quite tricky since the dumper has to effectively "interpret" the instructions. llvm-svn: 175820
* Allow GlobalValues to vectorize with AliasAnalysisRenato Golin2013-02-211-0/+356
| | | | | | | | | | | | | | | | | | | | | Storing the load/store instructions with the values and inspect them using Alias Analysis to make sure they don't alias, since the GEP pointer operand doesn't take the offset into account. Trying hard to not add any extra cost to loads and stores that don't overlap on global values, AA is *only* calculated if all of the previous attempts failed. Using biggest vector register size as the stride for the vectorization access, as we're being conservative and the cost model (which calculates the real vectorization factor) is only run after the legalization phase. We might re-think this relationship in the future, but for now, I'd rather be safe than sorry. llvm-svn: 175818
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+34
| | | | llvm-svn: 175783
* Make RAFast::UsedInInstr indexed by register units.Jakob Stoklund Olesen2013-02-211-0/+9
| | | | | | | | | | This fixes some problems with too conservative checking where we were marking all aliases of a register as used, and then also checking all aliases when allocating a register. <rdar://problem/13249625> llvm-svn: 175782
* Large code model support for PowerPC.Bill Schmidt2013-02-2110-94/+207
| | | | | | | | | | | Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. llvm-svn: 175767
* DAGCombiner: Make the post-legalize vector op optimization more aggressive.Benjamin Kramer2013-02-211-2/+0
| | | | | | | | A legal BUILD_VECTOR goes in and gets constant folded into another legal BUILD_VECTOR so we don't lose any legality here. The problematic PPC optimization that made this check necessary was fixed recently. llvm-svn: 175759
* R600: Fix for Unigine when MachineSched is enabledTom Stellard2013-02-211-0/+28
| | | | | | | | | | | Fixes for-loop.cl piglit test Patch By: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175742
* R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer2013-02-211-0/+23
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175733
* Expand the sel pseudo/macro. This generates basic blocks where previouslyReed Kotler2013-02-211-3/+3
| | | | | | | there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
* Mips specific standalone assembler addressing mode %hi and %lo.Jack Carter2013-02-212-3/+13
| | | | | | | | | | | | The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic llvm-svn: 175707
* PPCDAGToDAGISel::PostprocessISelDAG()Bill Schmidt2013-02-217-1/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual method to perform post-selection peephole optimizations on the DAG representation. One optimization is implemented here: folds to clean up complex addressing expressions for thread-local storage and medium code model. It will also be useful for large code model sequences when those are added later. I originally thought about doing this on the MI representation prior to register assignment, but it's difficult to do effective global dead code elimination at that point. DCE is trivial on the DAG representation. A typical example of a candidate code sequence in assembly: addis 3, 2, globalvar@toc@ha addi 3, 3, globalvar@toc@l lwz 5, 0(3) When the final instruction is a load or store with an immediate offset of zero, the offset from the add-immediate can replace the zero, provided the relocation information is carried along: addis 3, 2, globalvar@toc@ha lwz 5, globalvar@toc@l(3) Since the addi can in general have multiple uses, we need to only delete the instruction when the last use is removed. llvm-svn: 175697
* ELF symbol table field st_other support, Jack Carter2013-02-203-13/+182
| | | | | | | | | | | | | | | | | | | | excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
* Stabilize vec_constants.llBill Schmidt2013-02-201-1/+4
| | | | llvm-svn: 175683
* DAGCombiner: Fold pointless truncate, bitcast, buildvector seriesArnold Schwaighofer2013-02-201-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | (2xi32) (truncate ((2xi64) bitcast (buildvector i32 a, i32 x, i32 b, i32 y))) can be folded into a (2xi32) (buildvector i32 a, i32 b). Such a DAG would cause uneccessary vdup instructions followed by vmovn instructions. We generate this code on ARM NEON for a setcc olt, 2xf64, 2xf64. For example, in the vectorized version of the code below. double A[N]; double B[N]; void test_double_compare_to_double() { int i; for(i=0;i<N;i++) A[i] = (double)(A[i] < B[i]); } radar://13191881 Fixes bug 15283. llvm-svn: 175670
* Additional fixes for bug 15155.Bill Schmidt2013-02-202-14/+85
| | | | | | | | This handles the cases where the 6-bit splat element is odd, converting to a three-instruction sequence to add or subtract two splats. With this fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed. llvm-svn: 175663
* Fix PR15267Michael Liao2013-02-201-0/+66
| | | | | | | | | - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
* Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].Bill Schmidt2013-02-201-0/+99
| | | | | | | | The PPC backend doesn't handle these correctly. This patch uses logic similar to that in the X86 and ARM backends to track these arguments properly. llvm-svn: 175635
* Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.Jyotsna Verma2013-02-202-2/+59
| | | | | | | | Add HexagonMCInst class which adds various Hexagon VLIW annotations. In addition, this class also includes some APIs related to the constant extenders. llvm-svn: 175634
* Fix PR15155: lost vadd/vsplat optimization.Bill Schmidt2013-02-201-0/+77
| | | | | | | | | | | | | | During lowering of a BUILD_VECTOR, we look for opportunities to use a vector splat. When the splatted value fits in 5 signed bits, a single splat does the job. When it doesn't fit in 5 bits but does fit in 6, and is an even value, we can splat on half the value and add the result to itself. This last optimization hasn't been working recently because of improved constant folding. To circumvent this, create a pseudo VADD_SPLAT that can be expanded during instruction selection. llvm-svn: 175632
* I optimized the following patterns:Elena Demikhovsky2013-02-202-1/+34
| | | | | | | | | | | | | | | | sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619
* [asan] instrument invoke insns with noreturn attribute (as well as call insns)Kostya Serebryany2013-02-201-1/+22
| | | | llvm-svn: 175617
* Fix thumbv5e frame lowering assertion failure.Logan Chien2013-02-201-0/+29
| | | | | | | | | | | | | | It is possible that frame pointer is not found in the callee saved info, thus FramePtrSpillFI may be incorrect if we don't check the result of hasFP(MF). Besides, if we enable the stack coloring algorithm, there will be an assertion to ensure the slot is live. But in the test case, %var1 is not live in the prologue of the function, and we will get the assertion failure. Note: There is similar code in ARMFrameLowering.cpp. llvm-svn: 175616
* Use the attribute group reference instead of the attribute directly.Bill Wendling2013-02-201-1/+2
| | | | llvm-svn: 175609
* Modify the LLVM assembly output so that it uses references to represent ↵Bill Wendling2013-02-2027-148/+228
| | | | | | | | | | | function attributes. This makes the LLVM assembly look better. E.g.: define void @foo() #0 { ret void } attributes #0 = { nounwind noinline ssp } llvm-svn: 175605
* Expand pseudos/macros:Reed Kotler2013-02-2013-15/+15
| | | | | | | | SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
* [llvm-readobj] Add ELF .dynamic table dumping.Michael J. Spencer2013-02-201-0/+13
| | | | llvm-svn: 175592
* [ms-inline asm] Force the use of a base pointer if the MachineFunction includesChad Rosier2013-02-191-2/+2
| | | | | | | | | | | | | MS-style inline assembly. This is a follow-on to r175334. Forcing a FP to be emitted doesn't ensure it will be used. Therefore, force the base pointer as well. We now treat MS inline assembly in the same way we treat functions with dynamic stack realignment and VLAs. This guarantees the BP will be used to reference parameters and locals. rdar://13218191 llvm-svn: 175576
* ELF symbol table field st_other support, Jack Carter2013-02-191-7/+7
| | | | | | | | | | | | excluding visibility bits. Mips (o32 abi) specific e_header setting. EF_MIPS_ABI_O32 needs to be set in the ELF header flags for o32 abi output. Contributer: Reed Kotler llvm-svn: 175569
* ELF symbol table field st_other support, Jack Carter2013-02-192-2/+18
| | | | | | | | | | | | excluding visibility bits. Mips (Mips16) specific e_header setting. EF_MIPS_ARCH_ASE_M16 needs to be set in the ELF header flags for Mips16. Contributer: Reed Kotler llvm-svn: 175566
* Fix a bug in mayHaveSideEffects. Functions that do not return are now ↵Nadav Rotem2013-02-191-0/+18
| | | | | | | | considered as instructions with side effects. rdar://13227456 llvm-svn: 175553
* ARM: Allocation hints must make sure to be in the alloc order.Jim Grosbach2013-02-191-0/+53
| | | | | | | | | When creating an allocation hint for a register pair, make sure the hint for the physical register reference is still in the allocation order. rdar://13240556 llvm-svn: 175541
* Fix typoEli Bendersky2013-02-191-1/+1
| | | | llvm-svn: 175530
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