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* Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola2013-02-142-20/+6
| | | | llvm-svn: 175173
* Add testcase for llvm-dwarfdump to test parsing of the pubnames data.Krzysztof Parzyszek2013-02-143-0/+48
| | | | llvm-svn: 175168
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-146-153/+169
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Moved line-info.ll to DebugInfo\X86 directoryElena Demikhovsky2013-02-141-0/+0
| | | | llvm-svn: 175150
* The test failed on Windows. I've changed the platform to run to ↵Elena Demikhovsky2013-02-141-1/+1
| | | | | | "x86_64-apple-darwin". llvm-svn: 175146
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-0/+14
| | | | | | Added a test. llvm-svn: 175144
* R600: Add lit tests for texture sampling instruction selection.Michel Danzer2013-02-142-0/+113
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175138
* Reapply "s/grep/FileCheck/ in some tests"Andrew Trick2013-02-145-6/+15
| | | | | | | | This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85. Use a triple this time. llvm-svn: 175134
* Teach the DataLayout aware constant folder to be much more aggressive towardsNick Lewycky2013-02-141-0/+12
| | | | | | 'and' instructions. This is a pattern that shows up a lot in ubsan binaries. llvm-svn: 175128
* Revert "s/grep/FileCheck/ in some tests"Andrew Trick2013-02-145-16/+6
| | | | | | | | | | | | | | | | | | This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3. The FileCheck tests are not equivalent: test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input ; CHECK: jmp init ^ <stdin>:1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ <stdin>:13:2: note: possible intended match here jmp _init ## TAILCALL ^ llvm-svn: 175124
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-132-55/+2
| | | | llvm-svn: 175107
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+8
| | | | llvm-svn: 175102
* R600: Add support for 128-bit parametersTom Stellard2013-02-131-0/+18
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175096
* s/grep/FileCheck/ in some testsEli Bendersky2013-02-132-3/+5
| | | | llvm-svn: 175093
* s/grep/FileCheck/ in some testsEli Bendersky2013-02-135-6/+16
| | | | llvm-svn: 175089
* Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao2013-02-132-2/+55
| | | | | | on ARM llvm-svn: 175088
* [ms-inline asm] Fix up test case for non-Darwin platforms.Chad Rosier2013-02-131-1/+1
| | | | llvm-svn: 175087
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-132-0/+86
| | | | | | instead of redefining separate instructions for them. llvm-svn: 175086
* [ms-inline-asm] Add support for memory references that have non-immediateChad Rosier2013-02-131-0/+23
| | | | | | | displacements. rdar://12974533 llvm-svn: 175083
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-0/+31
| | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. llvm-svn: 175073
* Clean up LDV, no functionality change.Manman Ren2013-02-131-1/+1
| | | | | | | | Remove dead functions: renameRegister Move private member variables from LDV to Impl Remove ssp/uwtable from testing case llvm-svn: 175072
* PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto2013-02-131-0/+28
| | | | | | | Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. llvm-svn: 175066
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+18
| | | | | | | | | | | This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. llvm-svn: 175057
* Make jumptables work for -staticReed Kotler2013-02-131-0/+71
| | | | llvm-svn: 175044
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+40
| | | | | | since a caller uses preserved registers across the call. llvm-svn: 175043
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-0/+31
| | | | | | assembly. llvm-svn: 175036
* Finish obviously broken thought.Eric Christopher2013-02-131-1/+1
| | | | llvm-svn: 175035
* [tsan] disable load widening in ThreadSanitizer modeKostya Serebryany2013-02-131-0/+26
| | | | llvm-svn: 175034
* Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.Manman Ren2013-02-131-0/+173
| | | | | | | | | | | | | | RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs without emitting them at the end. We fix this by removing LDV from RegisterCoalescer. Also add an assertion to make sure we call emitDebugValues if DBG_VALUEs are removed at runOnMachineFunction. rdar://problem/13183203 Reviewed by Andy & Jakob llvm-svn: 175023
* Remove target-specific info from the testcase for DWARF/pubnames.Krzysztof Parzyszek2013-02-121-3/+0
| | | | llvm-svn: 174992
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-122-6/+20
| | | | | | | | | | | | | | This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 llvm-svn: 174983
* Allow optionally generating pubnames section in DWARF info. IntroduceKrzysztof Parzyszek2013-02-121-0/+127
| | | | | | option "generate-dwarf-pubnames" to control it, set to "false" by default. llvm-svn: 174981
* added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo2013-02-121-0/+6
| | | | llvm-svn: 174979
* Fix the lit test added in r174972Paul Redmond2013-02-121-2/+2
| | | | | | Patch by: Kevin Schoedel llvm-svn: 174974
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-0/+19
| | | | | | instructions. llvm-svn: 174973
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-121-0/+15
| | | | | | | | | | | DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem llvm-svn: 174972
* [NVPTX] Disable vector registersJustin Holewinski2013-02-121-0/+66
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. llvm-svn: 174968
* [asan] fix tests for the new ABIKostya Serebryany2013-02-122-4/+4
| | | | llvm-svn: 174959
* Test for string attributes and for attribute group output.Bill Wendling2013-02-121-0/+28
| | | | llvm-svn: 174954
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+40
| | | | | | | | | A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 llvm-svn: 174933
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-0/+27
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 llvm-svn: 174929
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-121-0/+26
| | | | | | Part of rdar://12470373 llvm-svn: 174926
* Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> ↵Michael Ilseman2013-02-111-1/+7
| | | | | | bitcast X to ... llvm-svn: 174905
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-117-0/+1528
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. llvm-svn: 174904
* Remove trailing whitespaceMichael Ilseman2013-02-111-7/+8
| | | | llvm-svn: 174903
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-0/+13
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture ↵Justin Holewinski2013-02-111-0/+21
| | | | | | is not valid in this case, and was causing incorrect optimizations. llvm-svn: 174896
* AArch64: generate dwarfdump test rather than include .o in subversionTim Northover2013-02-113-16/+33
| | | | llvm-svn: 174891
* AArch64: Add basic relocation processing for llvm-dwarfdump.Tim Northover2013-02-112-0/+16
| | | | | | | This allows llvm-dwarfdump to handle the relocations needed, at least for LLVM-produced code. llvm-svn: 174874
* AArch64: Undo change to how test was runTim Northover2013-02-111-1/+2
| | | | | | This broke on Windows, presumably due to interleaving of output streams. llvm-svn: 174873
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