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* [IRCE] Fix corner case with Start = INT_MAXMax Kazantsev2017-07-141-0/+117
| | | | | | | | | | | | | | | | | | | | When iterating through loop for (int i = INT_MAX; i > 0; i--) We fail to generate the pre-loop for it. It happens because we use the overflown value in a comparison predicate when identifying whether or not we need it. In old logic, we used SLE predicate against Greatest value which exceeds all seen values of the IV and might be overflown. Now we use the GreatestSeen value of this IV with SLT predicate. Also added a test that ensures that a pre-loop is generated for such loops. Differential Revision: https://reviews.llvm.org/D35347 llvm-svn: 308001
* AMDGPU: Detect kernarg segment pointerMatt Arsenault2017-07-149-25/+85
| | | | | | | | This is necessary to pass the kernarg segment pointer to callee functions. Also don't unconditionally enable for kernels. llvm-svn: 307978
* [AMDGPU] fcaninicalize optimization for GFX9+Stanislav Mekhanoshin2017-07-131-6/+56
| | | | | | | | | | | | | | Since GFX9 supports denorm modes for v_min_f32/v_max_f32 that is possible to further optimize fcanonicalize and remove it if applied to min/max given their operands are known not to be an sNaN or that sNaNs are not supported. Additionally we can remove fcanonicalize if denorms are supported for the VT and we know that its argument is never a NaN. Differential Revision: https://reviews.llvm.org/D35335 llvm-svn: 307976
* [DWARF] Introduce verification for the unit header chain in .debug_info ↵Spyridoula Gravani2017-07-131-0/+81
| | | | | | | | | | | | | | | section to llvm-dwarfdump. This patch adds verification checks for the unit header chain in the .debug_info section. Specifically, for each unit in the .debug_info section, the verifier checks that: The unit length is valid (i.e. the unit can actually fit in the .debug_info section) The dwarf version of the unit is valid The address size is valid (4 or 8) The unit type (if the unit is in dwarf5) is valid The debug_abbrev_offset is valid llvm-svn: 307975
* AMDGPU: Annotate call graph with used featuresMatt Arsenault2017-07-131-0/+200
| | | | | | | Previously this wouldn't detect used features indirectly used in callee functions. llvm-svn: 307967
* [InstCombine] put tests for commuted variants of the same fold together; NFCSanjay Patel2017-07-131-44/+66
| | | | llvm-svn: 307951
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-139-196/+25
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* [X86][tests] Added rotate_vec.ll CodeGen test. NFC precommit for bug 33691 fix.Andrew Zhogin2017-07-131-0/+60
| | | | llvm-svn: 307937
* [PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16Nemanja Ivanovic2017-07-135-50/+84
| | | | | | | | | | | | | As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 llvm-svn: 307934
* [InstCombine] add descriptive comments for tests; NFCSanjay Patel2017-07-131-9/+19
| | | | | | Also, remove unnecessary function attributes. llvm-svn: 307930
* [AArch64] Implement support for windows style vararg functionsMartin Storsjo2017-07-131-0/+95
| | | | | | | | | | | Pass parameters properly in calls to such functions (pass all floats in integer registers), and handle va_start properly (allocate stack immediately below the arguments on the stack, to save the register arguments into a single continuous array). Differential Revision: https://reviews.llvm.org/D35006 llvm-svn: 307928
* [llvm-objdump] Properly print MachO aarch64 addend relocationsMartin Storsjo2017-07-132-0/+6
| | | | | | | | | | Previously such relocations fell into the last case for local symbols, using the relocation addend as symbol index, leading to a crash. Differential Revision: https://reviews.llvm.org/D35239 llvm-svn: 307927
* [GlobalOpt] Autogenerate checks for the test in PR33686.Davide Italiano2017-07-131-5/+5
| | | | | | Also fix a typo while here. llvm-svn: 307921
* Reapply [GlobalOpt] Remove unreachable blocks before optimizing a function.Davide Italiano2017-07-131-0/+17
| | | | | | | This commit reapplies r307215 now that we found out and fixed the cause of the cfi test failure (in r307871). llvm-svn: 307920
* [AArch64] Enable the mnemonic spell checkerSjoerd Meijer2017-07-131-0/+37
| | | | | | | | | The AsmParser mnemonic spell checker was introduced in r307148 and enabled only for ARM. This patch enables it for AArch64. Differential Revision: https://reviews.llvm.org/D35357 llvm-svn: 307918
* [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomicsMatthew Simpson2017-07-131-0/+161
| | | | | | | This patch is a follow-up to r305893 and adds preliminary support for the fetch_sub and fetch_and operations. llvm-svn: 307913
* [RuntimeUnrolling] Update DomTree correctly when exit blocks have successorsAnna Thomas2017-07-131-0/+126
| | | | | | | | | | | | | | | | Summary: When we runtime unroll with multiple exit blocks, we also need to update the immediate dominators of the immediate successors of the exit blocks. Reviewers: reames, mkuper, mzolotukhin, apilipenko Reviewed by: mzolotukhin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35304 llvm-svn: 307909
* Reland "[mips] Fix multiprecision arithmetic."Simon Dardis2017-07-136-233/+444
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
* [ARM] GlobalISel: Support G_BRDiana Picus2017-07-133-0/+52
| | | | | | | | This boils down to not crashing in reg bank select due to the lack of register operands on this instruction, and adding some tests. The instruction selection is already covered by the TableGen'erated code. llvm-svn: 307904
* [DAGCombiner] Fix issue with rotate combines asserting if the constant value ↵Simon Pilgrim2017-07-131-0/+27
| | | | | | types differ from the result type. llvm-svn: 307900
* [ARM] Fix typo in test added in r307889Florian Hahn2017-07-131-1/+1
| | | | | | | | | This fixes the following test failure: LLVM :: Transforms/Inline/ARM/inline-target-attr.ll Sorry for any inconenience. llvm-svn: 307892
* [ARM] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-07-132-0/+62
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. As some subtarget features provide different instructions depending on whether they are set or unset (e.g. ThumbMode and ModeSoftFloat), we use a whitelist of target-features describing hardware capabilities only. Reviewers: kristof.beyls, rengolin, t.p.northover, SjoerdMeijer, peter.smith, silviu.baranga, efriedma Reviewed By: SjoerdMeijer, efriedma Subscribers: dschuff, efriedma, aemerson, sdardis, javed.absar, arichardson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34697 llvm-svn: 307889
* [AVR] Fix indirect calls to function pointersDylan McKay2017-07-131-0/+15
| | | | | | Patch by Carl Peto. llvm-svn: 307888
* Add original reproducer for r307754 / PR33689Mikael Holmen2017-07-131-0/+53
| | | | | | | Apparently I managed to drop the test case between two revisions in Phabricator: https://reviews.llvm.org/D35003 llvm-svn: 307887
* [llvm-objdump] Correctly distinguish between the MachO upper/lower16 relocationsMartin Storsjo2017-07-132-0/+4
| | | | | | | | | | All other code in MachODump.cpp uses the same comparison, ((r_length & 0x1) == 1), for distinguishing between the two, while the code in llvm-objdump.cpp seemed to be incorrect. Differential Revision: https://reviews.llvm.org/D35240 llvm-svn: 307882
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-132-0/+41
| | | | | | | | | | | | | | | | | Summary: Add target hooks for printing and parsing target MMO flags. Targets may override getSerializableMachineMemOperandTargetFlags() to return a mapping from string to flag value for target MMO values that should be serialized/parsed in MIR output. Add implementation of this hook for AArch64 SuppressPair MMO flag. Reviewers: bogner, hfinkel, qcolombet, MatzeB Subscribers: mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34962 llvm-svn: 307877
* [sanstats] Remove a flaky test.Davide Italiano2017-07-132-4/+0
| | | | | | | | | I don't know a reliable way of crafting a test for this case, but I'll try a little harder. In the meanwhile, let's get the bots green again. Please note this will be tested by `check-cfi` once r307215 relands. llvm-svn: 307874
* [DWARF] Fixing a bug with processing of DWARF v5 indexed strings in Mach-O ↵Wolfgang Pieb2017-07-133-73/+276
| | | | | | | | | | | objects. Code to convert MachO - specific section debug section names to standard DWARF v5 section names was in the wrong place. Differential Revision: https://reviews.llvm.org/D35321 llvm-svn: 307872
* [sanstats] Print the correct line information.Davide Italiano2017-07-132-0/+4
| | | | | | | | The instrumentation tracks the return address and not that of the call so we remove one to compensate. Thanks for Peter Collingbourne for confirming the analysis of the problem. llvm-svn: 307871
* [CodeGenPrepare] Don't create dead instructions in addrmode sinkingEli Friedman2017-07-121-0/+24
| | | | | | | | | | When we fail to sink an instruction, we must make sure not to modify the function; otherwise, we end up in an infinite loop because CodeGenPrepare iterates until it doesn't make any changes. Fixes https://bugs.llvm.org/show_bug.cgi?id=33608 . llvm-svn: 307866
* [PGO] Enhance pgo counter promotionXinliang David Li2017-07-123-4/+169
| | | | | | | | | | | | | | | | | | | | | | | This is an incremental change to the promotion feature. There are two problems with the current behavior: 1) loops with multiple exiting blocks are totally disabled 2) a counter update can only be promoted one level up in the loop nest -- which does help much for short trip count inner loops inside a high trip-count outer loops. Due to this limitation, we still saw very large profile count fluctuations from run to run for the affected loops which are usually very hot. This patch adds the support for promotion counters iteratively across the loop nest. It also turns on the promotion for loops with multiple exiting blocks (with a limit). For single-threaded applications, the performance impact is flat on average. For instance, dealII improves, but povray regresses. llvm-svn: 307863
* AMDGPU: Fix converting unanalyzable global loads to SMRDMatt Arsenault2017-07-121-0/+20
| | | | | | | Not all memory dependence queries succeed, so this needs to be conservative if it fails. llvm-svn: 307861
* [x86] add select-of-constant tests; NFCSanjay Patel2017-07-121-4/+109
| | | | | | We're using cmov in these cases, but we could reduce to simpler ops. llvm-svn: 307859
* Add element atomic memset intrinsicDaniel Neilson2017-07-122-0/+79
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
* [AMDGPU] fcanonicalize elimination optimizationStanislav Mekhanoshin2017-07-121-0/+487
| | | | | | | | | | | | We are using multiplication by 1.0 to flush denormals and quiet sNaNs. That is possible to omit this multiplication if source of the fcanonicalize instruction is known to be flushed/quieted, i.e. if it comes from another instruction known to do the normalization and we are using IEEE mode to quiet sNaNs. Differential Revision: https://reviews.llvm.org/D35218 llvm-svn: 307848
* [LoopUnrollRuntime] NFC: Refactored safety checks of unrolling multi-exit loopAnna Thomas2017-07-121-0/+68
| | | | | | | | | | | Refactored the code and separated out a function `canSafelyUnrollMultiExitLoop` to reduce redundant checks and make it easier to add profitability heuristics later. Added tests to runtime unrolling to make sure that unrolling for multi-exit loops is not done unless the option -unroll-runtime-multi-exit is true. llvm-svn: 307843
* [LV] Don't allow outside uses of IVs if the SCEV is predicated on loop ↵Michael Kuperstein2017-07-121-0/+61
| | | | | | | | | conditions. This fixes PR33706. Differential Revision: https://reviews.llvm.org/D35227 llvm-svn: 307837
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-129-25/+196
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* [LoopRotate] Fix DomTree update logic for unreachable nodes. Fix PR33701.Jakub Kuderski2017-07-121-0/+27
| | | | | | | | | | | | | | | | | | | Summary: LoopRotate manually updates the DoomTree by iterating over all predecessors of a basic block and computing the Nearest Common Dominator. When a predecessor happens to be unreachable, `DT.findNearestCommonDominator` returns nullptr. This patch teaches LoopRotate to handle this case and fixes [[ https://bugs.llvm.org/show_bug.cgi?id=33701 | PR33701 ]]. In the future, LoopRotate should be taught to use the new incremental API for updating the DomTree. Reviewers: dberlin, davide, uabelho, grosser Subscribers: efriedma, mzolotukhin Differential Revision: https://reviews.llvm.org/D35074 llvm-svn: 307828
* [x86] improve SBB optimizations for SETB/SETA with subtractSanjay Patel2017-07-121-5/+2
| | | | | | | | | | | | | | This is another step towards removing a combine that turns sext into select of constants and preparing the backend for an IR future where select is the canonical form. Earlier commits in this area: https://reviews.llvm.org/rL306040 https://reviews.llvm.org/rL306072 https://reviews.llvm.org/rL307404 (https://reviews.llvm.org/D34652) https://reviews.llvm.org/rL307471 llvm-svn: 307821
* [x86] add tests for improving sbb transforms; NFCSanjay Patel2017-07-121-0/+35
| | | | | | We're subtracting X from X the hard way... llvm-svn: 307819
* GlobalISel: Handle selection of G_IMPLICIT_DEF in AArch64Justin Bogner2017-07-121-0/+30
| | | | | | | | A generic variant of IMPLICIT_DEF was added in r306875, but this survives to selection and hits a `Cannot Select`. Add handling that converts the note to a regular IMPLICIT_DEF. llvm-svn: 307817
* Add a test for r307754George Burgess IV2017-07-121-0/+16
| | | | | | | | | | | As promised in D35003. Uses -codegenprepare instead of -instcombine since we hit the same buggy path anyway, and CGP lets us keep this test really simple (instcombine likes turning the alloca T, N into alloca [N x T], which hides the bug this is testing for). llvm-svn: 307811
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-123-1/+9
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* Add back a CHECK line.Rafael Espindola2017-07-121-0/+1
| | | | | | | | I accidentally removed it in r307730. Thanks to Martin Storsjö for noticing! llvm-svn: 307801
* [CodeGen] Add dependency printerEvandro Menezes2017-07-1212-52/+52
| | | | | | | | Add SDep printer to make debugging sessions more productive. Differential revision: https://reviews.llvm.org/D35144 llvm-svn: 307799
* [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats.Davide Italiano2017-07-121-0/+15
| | | | | | | | | | FastIsel can't handle them, so we would end up crashing during register class selection. Fixes PR26522. Differential Revision: https://reviews.llvm.org/D35272 llvm-svn: 307797
* Add element atomic memmove intrinsicDaniel Neilson2017-07-122-0/+87
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-124-0/+19
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [X86][SSE] Fix file check prefix warning breaking buildbotsSimon Pilgrim2017-07-122-4/+4
| | | | llvm-svn: 307790
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