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* Temporarily revert r250345 to sort out bot failure.Manman Ren2015-10-151-43/+0
| | | | | | | | | | | | | | With r250345 and r250343, we start to observe the following failure when bootstrap clang with lto and pgo: PHI node entries do not match predecessors! %.sroa.029.3.i = phi %"class.llvm::SDNode.13298"* [ null, %30953 ], [ null, %31017 ], [ null, %30998 ], [ null, %_ZN4llvm8dyn_castINS_14ConstantSDNodeENS_7SDValueEEENS_10cast_rettyIT_T0_E8ret_typeERS5_.exit.i.1804 ], [ null, %30975 ], [ null, %30991 ], [ null, %_ZNK4llvm3EVT13getScalarTypeEv.exit.i.1812 ], [ %..sroa.029.0.i, %_ZN4llvm11SmallVectorIiLj8EED1Ev.exit.i.1826 ], !dbg !451895 label %30998 label %_ZNK4llvm3EVTeqES0_.exit19.thread.i LLVM ERROR: Broken function found, compilation aborted! I will re-commit this if the bot does not recover. llvm-svn: 250366
* s/NumFiles/NumStreams/David Majnemer2015-10-151-1/+1
| | | | llvm-svn: 250357
* [llvm-pdbdump] Provide a mechanism to dump the raw contents of a PDBDavid Majnemer2015-10-154-7/+19
| | | | | | | | | A PDB can be thought of as a very simple file system. It is occasionally illuminating to see the contents of the underlying files. Differential Revision: http://reviews.llvm.org/D13674 llvm-svn: 250356
* [ARM] Make sure we do not dereference the end iterator when accessing debugQuentin Colombet2015-10-151-0/+57
| | | | | | | | | | information. Although the problem was always here, it would only be exposed when shrink-wrapping is enable. rdar://problem/23110493 llvm-svn: 250352
* Revert r250349.Akira Hatanaka2015-10-155-144/+4
| | | | | | Test case coal-sections-powerpc.s is still failing on some buildbots. llvm-svn: 250351
* [MachO] Stop generating *coal* sections.Akira Hatanaka2015-10-145-4/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommit r250342: add -arch=ppc32 to the RUN lines of powerpc tests. Some background on why we don't have to use *coal* sections anymore: Long ago when C++ was new and "weak" had not been standardized, an attempt was made in cctools to support C++ inlines that can be coalesced by putting them into their own section (TEXT/textcoal_nt instead of TEXT/text). The current macho linker supports the weak-def bit on any symbol to allow it to be coalesced, but the compiler still puts weak-def functions/data into alternate section names, which the linker must map back to the base section name. This patch makes changes that are necessary to prevent the compiler from using the "coal" sections and have it use the non-coal sections instead when the target architecture is not powerpc: TEXT/textcoal_nt instead use TEXT/text TEXT/const_coal instead use TEXT/const DATA/datacoal_nt instead use DATA/data If the target is powerpc, we continue to use the *coal* sections since anyone targeting powerpc is probably using an old linker that doesn't have support for the weak-def bits. Also, have the assembler issue a warning if it encounters a *coal* section in the assembly file and inform the users to use the non-coal sections instead. rdar://problem/14265330 Differential Revision: http://reviews.llvm.org/D13188 llvm-svn: 250349
* Revert r250342.Akira Hatanaka2015-10-145-144/+4
| | | | | | Investigate why coal-sections-powerpc.s is failing on some buildbots. llvm-svn: 250346
* Update the branch weight metadata in JumpThreading pass.Cong Hou2015-10-141-0/+43
| | | | | | | | | | Currently in JumpThreading pass, the branch weight metadata is not updated after CFG modification. Consider the jump threading on PredBB, BB, and SuccBB. After jump threading, the weight on BB->SuccBB should be adjusted as some of it is contributed by the edge PredBB->BB, which doesn't exist anymore. This patch tries to update the edge weight in metadata on BB->SuccBB by scaling it by 1 - Freq(PredBB->BB) / Freq(BB->SuccBB). This is the third attempt to submit this patch, while the first two led to failures in some FDO tests. After investigation, it is the edge weight normalization that caused those failures. In this patch the edge weight normalization is fixed so that there is no zero weight in the output and the sum of all weights can fit in 32-bit integer. Several unit tests are added. Differential revision: http://reviews.llvm.org/D10979 llvm-svn: 250345
* Test case which should have been part of 250343Philip Reames2015-10-141-0/+86
| | | | llvm-svn: 250344
* [MachO] Stop generating *coal* sections.Akira Hatanaka2015-10-145-4/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some background on why we don't have to use *coal* sections anymore: Long ago when C++ was new and "weak" had not been standardized, an attempt was made in cctools to support C++ inlines that can be coalesced by putting them into their own section (TEXT/textcoal_nt instead of TEXT/text). The current macho linker supports the weak-def bit on any symbol to allow it to be coalesced, but the compiler still puts weak-def functions/data into alternate section names, which the linker must map back to the base section name. This patch makes changes that are necessary to prevent the compiler from using the "coal" sections and have it use the non-coal sections instead when the target architecture is not powerpc: TEXT/textcoal_nt instead use TEXT/text TEXT/const_coal instead use TEXT/const DATA/datacoal_nt instead use DATA/data If the target is powerpc, we continue to use the *coal* sections since anyone targeting powerpc is probably using an old linker that doesn't have support for the weak-def bits. Also, have the assembler issue a warning if it encounters a *coal* section in the assembly file and inform the users to use the non-coal sections instead. rdar://problem/14265330 Differential Revision: http://reviews.llvm.org/D13188 llvm-svn: 250342
* Tighten known bits for ctpop based on zero input bitsPhilip Reames2015-10-141-0/+45
| | | | | | | | | | This is a cleaned up patch from the one written by John Regehr based on the findings of the Souper superoptimizer. The basic idea here is that input bits that are known zero reduce the maximum count that the intrinsic could return. We know that the number of bits required to represent a particular count is at most log2(N)+1. Differential Revision: http://reviews.llvm.org/D13253 llvm-svn: 250338
* add x86 codegen tests for 'add nsw' followed by 'sext'Sanjay Patel2015-10-141-0/+179
| | | | llvm-svn: 250332
* [PowerPC] Fix invalid lxvdsx optimization (PR25157)Bill Schmidt2015-10-141-0/+58
| | | | | | | | | | | | PR25157 identifies a bug where a load plus a vector shuffle is incorrectly converted into an LXVDSX instruction. That optimization is only valid if the load is of a doubleword, and in the noted case, it was not. This corrects that problem. Joint patch with Eric Schweitz, who provided the bugpoint-reduced test case. llvm-svn: 250324
* [llvm-readobj/ELF] fix: add correct test inputsIgor Kudrin2015-10-144-0/+0
| | | | llvm-svn: 250292
* [llvm-readobj/ELF] Print GNU Hash sectionIgor Kudrin2015-10-145-0/+63
| | | | | | | | Add a new command line switch, -gnu-hash-table, to print the content of that section. Differential Revision: http://reviews.llvm.org/D13696 llvm-svn: 250291
* [x86][FastISel] Teach how to select nontemporal stores.Andrea Di Biagio2015-10-141-0/+69
| | | | | | | | | | | | | | | | | | | | | | This patch teaches x86 fast-isel how to select nontemporal stores. On x86, we can use MOVNTI for nontemporal stores of doublewords/quadwords. Instructions (V)MOVNTPS/PD/DQ can be used for SSE2/AVX aligned nontemporal vector stores. Before this patch, fast-isel always selected 'movd/movq' instead of 'movnti' for doubleword/quadword nontemporal stores. In the case of nontemporal stores of aligned vectors, fast-isel always selected movaps/movapd/movdqa instead of movntps/movntpd/movntdq. With this patch, if we use SSE2/AVX intrinsics for nontemporal stores we now always get the expected (V)MOVNT instructions. The lack of fast-isel support for nontemporal stores was spotted when analyzing the -O0 codegen for nontemporal stores. Differential Revision: http://reviews.llvm.org/D13698 llvm-svn: 250285
* Add a instrumentation test for LinuxXinliang David Li2015-10-141-0/+1
| | | | | | Make sure __llvm_profile_init is not emitted. llvm-svn: 250274
* Revert r250204 and r250240 due to bot failure. We failed to build PGO-ed clang.Manman Ren2015-10-141-43/+0
| | | | llvm-svn: 250264
* [msan] Fix crash on multiplication by a non-integer constant.Evgeniy Stepanov2015-10-141-0/+23
| | | | | | Fixes PR25160. llvm-svn: 250260
* [asan] Disabling speculative loads under asan. Patch by Mike AizatskyKostya Serebryany2015-10-141-0/+40
| | | | llvm-svn: 250259
* Sample profiles - Add a name table to the binary encoding.Diego Novillo2015-10-131-0/+0
| | | | | | | | Binary encoded profiles used to encode all function names inline at every reference. This is clearly suboptimal in terms of space. This patch fixes this by adding a name table to the header of the file. llvm-svn: 250241
* Update MachineBranchProbabilityInfo::normalizeEdgeWeights to make sure there ↵Cong Hou2015-10-131-0/+43
| | | | | | | | is no zero weight in the output, and also add a missing test for JumpThreading. The test is for the patch in http://reviews.llvm.org/D10979 but was missing when committing that patch. llvm-svn: 250240
* [InlineFunction] Correctly inline TerminatePadInstDavid Majnemer2015-10-131-0/+54
| | | | | | | | | | | We forgot to append the terminatepad's arguments which resulted in us treating the old terminatepad as an argument to the new terminatepad causing us to crash immediately. Instead, add the old terminatepad's arguments to the new terminatepad. This fixes PR25155. llvm-svn: 250234
* Tweak to r250117 and change to use ErrorOr and drop isSizeValid forKevin Enderby2015-10-131-7/+0
| | | | | | | | | | ArchiveMemberHeader, suggestion by Rafael Espíndola. Also The clang-x86-win2008-selfhost bot still does not like the malformed-machos 00000031.a test, so removing it for now. All the other bots are fine with it however. llvm-svn: 250222
* [WinEH] Add CoreCLR EH table emissionJoseph Tremoulet2015-10-131-0/+239
| | | | | | | | | | | | | | | | | | Summary: Emit the handler and clause locations immediately after the standard xdata. Clauses are emitted in the same order and format used to communiate them to the CLR Execution Engine. Add a lit test to verify correct table generation on a small but interesting example function. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: pgavlin, AndyAyers, llvm-commits Differential Revision: http://reviews.llvm.org/D13451 llvm-svn: 250219
* [AArch64] Check the size of the vector before accessing its elements.Akira Hatanaka2015-10-131-0/+9
| | | | | | | | This fixes an assert in AArch64AsmParser::MatchAndEmitInstruction. rdar://problem/23081753 llvm-svn: 250207
* [PGO]: Eliminate calls to __llvm_profile_register_function for Linux.Xinliang David Li2015-10-131-4/+7
| | | | | | | | | On Linux, the profile runtime can use __start_SECTNAME and __stop_SECTNAME symbols defined by the linker to locate the start and end location of a named section (with C name). This eliminates the need for instrumented binary to call __llvm_profile_register_function during start-up time. llvm-svn: 250199
* The issue with the malformed-machos 00000031.a test is that it needed ↵Kevin Enderby2015-10-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ‘-arch x86_64’ flag as it was a Mach-O universal file. The default as to which architecture slice that is dumped without an -arch flag depends on the host architecture and the contents of the universal file. The malformed archive 00000031.a file has both an x86_64 and i386 slice. So for for x86_64 hosts only that slice is dumped, for non-x86_64 hosts, which is many of the bots both slices are dumped. The test is intended to only check that the malformation of the x86_64 which has a non-decimal characters in the size field of the archive header so it no longer crashes. The problem turned out that the i388 slice of the malformed archive had a different malformation which was causing the non-x86_64 bots to get this error: llvm-objdump -macho -disassemble -arch i386 00000031.a Archive : .00000031.a 00000031.a(c_start.o): LLVM ERROR: Symbol name entry points before beginning or past end of file. and causing the test as it was written to fail. So by adding ‘-arch x86_64’ it should correct the test and the malformation on the i388 slice will not be dumped. Also the removal of the malformed-machos mem-crup-0261.macho was not causing the issue so that is put back in. Sorry for the churn on these tests, Kev llvm-svn: 250184
* [InstCombine][SSE4A] Remove broken INSERTQI range combining optimizationSimon Pilgrim2015-10-131-85/+0
| | | | | | | | As discussed in D13348 - the INSERTQI range combining code is wrong in that it confuses the insertion bit index with an extraction bit index. The remaining legal combines are very unlikely (especially once we've converted to shuffles in D13348) so I'm removing the optimization. llvm-svn: 250160
* [GlobalsAA] Don't assume anything about functions that may be overriddenJames Molloy2015-10-131-0/+24
| | | | | | | | Weak linkage and friends allow a symbol to be overriden outside the code generator's model, so GlobalsAA shouldn't assume that anything it can compute about such a symbol is valid. llvm-svn: 250156
* Revert 250089 due to bot failure. It failed when building clang itself with PGO.Manman Ren2015-10-131-43/+0
| | | | llvm-svn: 250145
* Looks like malformed-machos 00000031.a test is just getting a different errorKevin Enderby2015-10-131-6/+0
| | | | | | on some of the bots. I’ll remove this test for now. llvm-svn: 250141
* DAGCombiner: Don't stop finding better chain on 2 aliasesMatt Arsenault2015-10-131-22/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | The comment says this was stopped because it was unlikely to be profitable. This is not true if you want to combine vector loads with multiple components. For a simple case that looks like t0 = load t0 ... t1 = load t0 ... t2 = load t0 ... t3 = load t0 ... t4 = store t0:1, t0:1 t5 = store t4, t1:0 t6 = store t5, t2:0 t7 = store t6, t3:0 We want to get all of these stores onto a chain that is a TokenFactor of these N loads. This mostly solves the AMDGPU merge-stores.ll regressions with -combiner-alias-analysis for merging vector stores of vector loads. llvm-svn: 250138
* x86: preserve flags when folding atomic operationsJF Bastien2015-10-131-0/+38
| | | | | | | | | | | | | | | | | | | | | Summary: D4796 taught LLVM to fold some atomic integer operations into a single instruction. The pattern was unaware that the instructions clobbered flags. This patch adds the missing EFLAGS definition. Floating point operations don't set flags, the subsequent fadd optimization is therefore correct. The same applies for surrounding load/store optimizations. Reviewers: rsmith, rtrieu Subscribers: llvm-commits, reames, morisset Differential Revision: http://reviews.llvm.org/D13680 llvm-svn: 250135
* Remove the correct unstable malformed-machos test mem-crup-0261.macho andKevin Enderby2015-10-131-3/+6
| | | | | | | restore the malformed-machos 00000031.a test. Hopefully this will get all the build bots happy again. I’ll again keep an eye on them. llvm-svn: 250130
* DAGCombiner: Combine extract_vector_elt from build_vectorMatt Arsenault2015-10-125-28/+39
| | | | | | | | | | | | | | This basic combine was surprisingly missing. AMDGPU legalizes many operations in terms of 32-bit vector components, so not doing this results in many extra copies and subregister extracts that need to be cleaned up later. InstCombine already does this for the hasOneUse case. The target hook is to fix a handful of tests which break (e.g. ARM/vmov.ll) which turn from a vector materialize repeated immediate instruction to a constant vector load with more scalar copies from it. llvm-svn: 250129
* [InstCombine] Tidied up SSE4A tests.Simon Pilgrim2015-10-121-37/+39
| | | | | | First stage of bugfix discussed in D13348 llvm-svn: 250121
* Temporarily remove the test added in r250117 while I investigate why twoKevin Enderby2015-10-121-6/+0
| | | | | | of the build bots get a different error on that malformed file. llvm-svn: 250120
* Assign correct edge weights to unwind destinations when lowering invoke ↵Cong Hou2015-10-124-9/+94
| | | | | | | | | | statement. When lowering invoke statement, all unwind destinations are directly added as successors of call site block, and the weight of those new edges are not assigned properly. Actually, default weight 16 are used for those edges. This patch calculates the proper edge weights for those edges when collecting all unwind destinations. Differential revision: http://reviews.llvm.org/D13354 llvm-svn: 250119
* Fixed bugs in llvm-obdump while parsing Mach-O files from malformed archivesKevin Enderby2015-10-122-0/+6
| | | | | | | | | that caused aborts. This was because of the characters of the ‘Size’ field in the archive header did not contain decimal characters. rdar://22983603 llvm-svn: 250117
* Update the branch weight metadata in JumpThreading pass.Cong Hou2015-10-121-0/+43
| | | | | | | | In JumpThreading pass, the branch weight metadata is not updated after CFG modification. Consider the jump threading on PredBB, BB, and SuccBB. After jump threading, the weight on BB->SuccBB should be adjusted as some of it is contributed by the edge PredBB->BB, which doesn't exist anymore. This patch tries to update the edge weight in metadata on BB->SuccBB by scaling it by 1 - Freq(PredBB->BB) / Freq(BB->SuccBB). Differential revision: http://reviews.llvm.org/D10979 llvm-svn: 250089
* Make Win64 localescape offsets FP relative instead of SP relativeReid Kleckner2015-10-121-18/+33
| | | | | | | | | We made them SP relative back in March (r233137) because that's the value the runtime passes to EH functions. With the new cleanuppad IR, funclets adjust their frame argument from SP to FP, so our offsets should now be FP-relative. llvm-svn: 250088
* [llvm-symbolizer] Add -print-address optionHemant Kulkarni2015-10-123-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D13518 llvm-svn: 250086
* [x86] Fix wrong lowering of vsetcc nodes (PR25080).Andrea Di Biagio2015-10-121-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function LowerVSETCC (in X86ISelLowering.cpp) worked under the wrong assumption that for non-AVX512 targets, the source type and destination type of a type-legalized setcc node were always the same type. This assumption was unfortunately incorrect; the type legalizer is not always able to promote the return type of a setcc to the same type as the first operand of a setcc. In the case of a vsetcc node, the legalizer firstly checks if the first input operand has a legal type. If so, then it promotes the return type of the vsetcc to that same type. Otherwise, the return type is promoted to the 'next legal type', which, for vectors of MVT::i1 is always a 128-bit integer vector type. Example (-mattr=+avx): %0 = trunc <8 x i32> %a to <8 x i23> %1 = icmp eq <8 x i23> %0, zeroinitializer The initial selection dag for the code above is: v8i1 = setcc t5, t7, seteq:ch t5: v8i23 = truncate t2 t2: v8i32,ch = CopyFromReg t0, Register:v8i32 %vreg1 t7: v8i32 = build_vector of all zeroes. The type legalizer would firstly check if 't5' has a legal type. If so, then it would reuse that same type to promote the return type of the setcc node. Unfortunately 't5' is of illegal type v8i23, and therefore it cannot be used to promote the return type of the setcc node. Consequently, the setcc return type is promoted to v8i16. Later on, 't5' is promoted to v8i32 thus leading to the following dag node: v8i16 = setcc t32, t25, seteq:ch where t32 and t25 are now values of type v8i32. Before this patch, function LowerVSETCC would have wrongly expanded the setcc to a single X86ISD::PCMPEQ. Surprisingly, ISel was still able to match an instruction. In our case, ISel would have matched a VPCMPEQWrr: t37: v8i16 = X86ISD::VPCMPEQWrr t36, t25 However, t36 and t25 are both VR256, while the result type is instead of class VR128. This inconsistency ended up causing the insertion of COPY instructions like this: %vreg7<def> = COPY %vreg3; VR128:%vreg7 VR256:%vreg3 Which is an invalid full copy (not a sub register copy). Eventually, the backend would have hit an UNREACHABLE "Cannot emit physreg copy instruction" in the attempt to expand the malformed pseudo COPY instructions. This patch fixes the problem adding the missing logic in LowerVSETCC to handle the corner case of a setcc with 128-bit return type and 256-bit operand type. This problem was originally reported by Dimitry as PR25080. It has been latent for a very long time. I have added the minimal reproducible from that bugzilla as test setcc-lowering.ll. Differential Revision: http://reviews.llvm.org/D13660 llvm-svn: 250085
* [llvm-symbolizer] Reverting r250067Colin LeMahieu2015-10-122-20/+0
| | | | llvm-svn: 250072
* [llvm-symbolizer] Add -print-address optionHemant Kulkarni2015-10-122-0/+20
| | | | | | Differential Revision http://reviews.llvm.org/D13518 llvm-svn: 250067
* [mips][micromips] Initial support for micrmomips DSP instructions and ↵Zoran Jovanovic2015-10-122-0/+9
| | | | | | | | addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
* [Debug] Look through bitcasts to find argument registersOliver Stannard2015-10-121-0/+45
| | | | | | | | | | On targets where f32 is not legal, we have to look through a BITCAST SDNode to find the register that an argument is stored in when emitting debug info, or we will not be able to emit a DW_AT_location for it. Differential Revision: http://reviews.llvm.org/D13005 llvm-svn: 250056
* [AArch64]Fix bug in function names in test caseJun Bum Lim2015-10-121-4/+4
| | | | | | | Functions in this test case need to be renamed as its names are the same as the instructions we are comparing with. llvm-svn: 250052
* [mips][ias] Implement macro expansion when bcc has an immediate where a ↵Daniel Sanders2015-10-122-0/+81
| | | | | | | | | | | | | | register belongs. Summary: Fixes PR24915. Reviewers: vkalintiris Subscribers: emaste, seanbruno, llvm-commits Differential Revision: http://reviews.llvm.org/D13533 llvm-svn: 250042
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