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* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-11-051-0/+44
| | | | | | Differential Revision: http://reviews.llvm.org/D5933 llvm-svn: 221352
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-052-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-05236-4889/+4889
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
* R600/SI: Add an extra check line to make test more strictTom Stellard2014-11-051-0/+1
| | | | llvm-svn: 221349
* [X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.Andrea Di Biagio2014-11-051-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch improves the folding of vector AND nodes into blend operations for targets that feature SSE4.1. A vector AND node where one of the operands is a constant build_vector with elements that are either zero or all-ones can be converted into a blend. This allows for example to simplify the following code: define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) { %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> %2 = and <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 0> %3 = or <4 x i32> %1, %2 ret <4 x i32> %3 } Before this patch llc (-mcpu=corei7) generated: andps LCPI1_0(%rip), %xmm0, %xmm0 andps LCPI1_1(%rip), %xmm1, %xmm1 orps %xmm1, %xmm0, %xmm0 retq With this patch we generate a single 'vpblendw'. llvm-svn: 221343
* Fix bashism in tests added by r221341Oliver Stannard2014-11-052-4/+4
| | | | llvm-svn: 221342
* [ARM] Honor FeatureD16 in the assembler and disassemblerOliver Stannard2014-11-054-7/+54
| | | | | | | | | | | | | | | Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341
* Improve logic that decides if its profitable to commute when some of the ↵Craig Topper2014-11-059-77/+42
| | | | | | virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves. llvm-svn: 221336
* llvm/test/Transforms/GCOVProfiling: Avoid to parse backslashes in MDString. ↵NAKAMURA Takumi2014-11-053-9/+3
| | | | | | | | | | | | | Use %/T instead of %T. LLVM Parser decodes "\bb" as hex in "C:\bb-win7\buildername\build...", with MDString. See also, http://llvm.org/docs/LangRef.html#metadata-nodes-and-metadata-strings This reverts r221270, "Disable 3 tests in llvm/test/Transforms/GCOVProfiling/ for now. Investigating." FIXME: Please check EC in GCOVProfiler::emitProfileNotes(). llvm-svn: 221334
* llvm-readobj: Add support for dumping the DOS header in PE filesDavid Majnemer2014-11-051-0/+19
| | | | llvm-svn: 221333
* InstSimplify: Exact shifts of X by Y are X if X has the lsb setDavid Majnemer2014-11-051-0/+14
| | | | | | | | | Exact shifts may not shift out any non-zero bits. Use computeKnownBits to determine when this occurs and just return the left hand side. This fixes PR21477. llvm-svn: 221325
* ARM: try to add extra CS-register whenever stack alignment >= 8.Tim Northover2014-11-051-2/+2
| | | | | | | | | | We currently try to push an even number of registers to preserve 8-byte alignment during a function's prologue, but only when the stack alignment is prcisely 8. Many of the reasons for doing it apply also when that alignment > 8 (the extra store is often free, and can save another stack adjustment, though less frequently for 16-byte stack alignment). llvm-svn: 221321
* ARM/Dwarf: correctly align stack before callee-saved VPRsTim Northover2014-11-051-0/+68
| | | | | | | | | | | | | | | | | | We were making an attempt to do this by adding an extra callee-saved GPR (so that there was an even number in the list), but when that failed we went ahead and pushed anyway. This had a couple of potential issues: + The .cfi directives we emit misplaced dN because they were based on PrologEpilogInserter's calculation. + Unaligned stores can be less efficient. + Unaligned stores can actually fault (likely only an issue in niche cases, but possible). This adds a final explicit stack adjustment if all other options fail, so that the actual locations of the registers match up with where they should be. llvm-svn: 221320
* Analysis: Make isSafeToSpeculativelyExecute fire less for dividesDavid Majnemer2014-11-041-6/+4
| | | | | | | | | | | | | Divides and remainder operations do not behave like other operations when they are given poison: they turn into undefined behavior. It's really hard to know if the operands going into a div are or are not poison. Because of this, we should only choose to speculate if there are constant operands which we can easily reason about. This fixes PR21412. llvm-svn: 221318
* Revert "[Reassociate] Canonicalize negative constants out of expressions."Reid Kleckner2014-11-043-236/+70
| | | | | | | | | | | | This reverts commit r221171. It performs this invalid transformation: - %div.i = urem i64 -1, %add - %sub.i = sub i64 -2, %div.i + %div.i = urem i64 1, %add + %sub.i1 = add i64 %div.i, -2 llvm-svn: 221317
* [X86][SSE] Enable commutation for SSE immediate blend instructionsSimon Pilgrim2014-11-046-82/+170
| | | | | | | | | | Patch to allow (v)blendps, (v)blendpd, (v)pblendw and vpblendd instructions to be commuted - swaps the src registers and inverts the blend mask. This is primarily to improve memory folding (see new tests), but it also improves the quality of shuffles (see modified tests). Differential Revision: http://reviews.llvm.org/D6015 llvm-svn: 221313
* [AArch64] Use the correct register class for ORR.Juergen Ributzka2014-11-041-1/+18
| | | | | | | | | While fixing up the register classes in the machine combiner in a previous commit I missed one. This fixes the last one and adds a test case. llvm-svn: 221308
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-048-227/+6
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* Provide gmlt-like inline scope information in the skeleton CU to facilitate ↵David Blaikie2014-11-042-1/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | symbolication without needing the .dwo files Clang -gsplit-dwarf self-host -O0, binary increases by 0.0005%, -O2, binary increases by 25%. A large binary inside Google, split-dwarf, -O0, and other internal flags (GDB index, etc) increases by 1.8%, optimized build is 35%. The size impact may be somewhat greater in .o files (I haven't measured that much - since the linked executable -O0 numbers seemed low enough) due to relocations. These relocations could be removed if we taught the llvm-symbolizer to handle indexed addressing in the .o file (GDB can't cope with this just yet, but GDB won't be reading this info anyway). Also debug_ranges could be shared between .o and .dwo, though ideally debug_ranges would get a schema that could used index(+offset) addressing, and move to the .dwo file, then we'd be back to sharing addresses in the address pool again. But for now, these sizes seem small enough to go ahead with this. Verified that no other DW_TAGs are produced into the .o file other than subprograms and inlined_subroutines. llvm-svn: 221306
* Don't produce relocations for a difference in a section with no symbols.Rafael Espindola2014-11-042-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were producing a relocation for ---------------- .section foo,bar La: Lb: .long La-Lb -------------- but not for --------------------- .section foo,bar zed: La: Lb: .long La-Lb ---------------- This patch handles the case where both fragments are part of the first atom in a section and there is no corresponding symbol to that atom. This fixes pr21328. llvm-svn: 221304
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-048-6/+227
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [PBQP] Callee saved regs should have a higher cost than scratch regsArnaud A. de Grandmaison2014-11-041-0/+91
| | | | | | | | | | | Registers are not all equal. Some are not allocatable (infinite cost), some have to be preserved but can be used, and some others are just free to use. Ensure there is a cost hierarchy reflecting this fact, so that the allocator will favor scratch registers over callee-saved registers. llvm-svn: 221293
* AArch64: Pattern match integer vector abs like we do on ARM.Benjamin Kramer2014-11-041-0/+70
| | | | | | This kind of pattern is emitted by the loop vectorizer. llvm-svn: 221289
* [mips] Improve support for the .set mips16/nomips16 assembler directives.Toma Tabacu2014-11-041-0/+10
| | | | | | | | | | | | | | | | | | | Summary: Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted). These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled). Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5462 llvm-svn: 221277
* [Stackmaps] Make test less fragile. NFC.Juergen Ributzka2014-11-041-2/+2
| | | | llvm-svn: 221276
* Disable 3 tests in llvm/test/Transforms/GCOVProfiling/ for now. Investigating.NAKAMURA Takumi2014-11-043-0/+6
| | | | llvm-svn: 221270
* Remove "REQUIRES:shell" from tests. They work for me.NAKAMURA Takumi2014-11-047-12/+0
| | | | llvm-svn: 221269
* [yaml2obj] Allow yaml2obj tool to recognize EF_MIPS_NAN2008 flagSimon Atanasyan2014-11-041-2/+4
| | | | llvm-svn: 221268
* Re-enable tests in llvm/test/Object, corresponding to line_iterator'sNAKAMURA Takumi2014-11-045-15/+0
| | | | | | change in r221153. llvm-svn: 221265
* llvm/test/Transforms/GCOVProfiling/linezero.ll: Use %/T instead of %T in ↵NAKAMURA Takumi2014-11-041-2/+1
| | | | | | regex. This works on win32. llvm-svn: 221262
* Add missing tests for build attribute encodings in object files.Charlie Turner2014-11-041-17/+106
| | | | | | | | | test/MC/ARM/directive-eabi_attribute.s was missing several tests of object file encodings relative to the existing tests for assembly file encodings. This commit adds the missing tests. Change-Id: Ie110ca02b65e8f4d4c77f437bd09d03607fa5c0d llvm-svn: 221250
* CodeGen: Enable DWARF emission for MS ABI targetsDavid Majnemer2014-11-045-52/+64
| | | | | | | | | | | | | | This is experimental, just barely enough to get things to not immediately combust. A note for those who are curious: Only lld can successfully link the object files, other linkers truncate the section names making the debug sections illegible to debuggers. Even with this in mind, we believe we are having trouble with SECREL relocations. llvm-svn: 221245
* test: Restore llvm-lit (at least for my machine)David Majnemer2014-11-041-16/+19
| | | | | | r221137 feeds None into os.path.join which is not valid. llvm-svn: 221242
* Minimize test case furtherDavid Majnemer2014-11-041-24/+17
| | | | | | No functional change intended. llvm-svn: 221237
* Revert "Transforms: reapply SVN r219899"Reid Kleckner2014-11-045-92/+38
| | | | | | | This reverts commit r220811 and r220839. It made an incorrect change to musttail handling. llvm-svn: 221226
* The patchpoint lowering logic would crash with live constants equal toSanjoy Das2014-11-041-0/+83
| | | | | | | the tombstone or empty keys of a DenseMap<int64_t, T>. This patch fixes the issue (and adds a tests case). llvm-svn: 221214
* Add the code and test cases for 32-bit Intel to llvm-objdump’s Mach-O ↵Kevin Enderby2014-11-044-0/+17
| | | | | | symbolizer. llvm-svn: 221211
* [Hexagon] Reverting 220584 to address ASAN errors.Colin LeMahieu2014-11-042-7/+0
| | | | llvm-svn: 221210
* Use AA in LoadCombineHal Finkel2014-11-032-0/+83
| | | | | | | | | | | | | | LoadCombine can be smarter about aborting when a writing instruction is encountered, instead of aborting upon encountering any writing instruction, use an AliasSetTracker, and only abort when encountering some write that might alias with the loads that could potentially be combined. This was originally motivated by comments made (and a test case provided) by David Majnemer in response to PR21448. It turned out that LoadCombine was not responsible for that PR, but LoadCombine should also be improved so that unrelated stores (and @llvm.assume) don't interrupt load combining. llvm-svn: 221203
* Handle ASAN_OPTIONS and UBSAN_OPTIONS in TestingConfig.pyRafael Espindola2014-11-031-5/+0
| | | | | | | | Currently they are passed to tests of llvm itself, but not, for example, lld. With this patch the options are visible in every test. llvm-svn: 221198
* InstCombine: Remove infinite loop caused by FoldOpIntoPhiDavid Majnemer2014-11-032-16/+23
| | | | | | | | | | | | | | FoldOpIntoPhi could create an infinite loop if the PHI could potentially reach a BB it was considering inserting instructions into. The instructions it would insert would eventually lead to other combines firing which would, again, lead to FoldOpIntoPhi firing. The solution is to handicap FoldOpIntoPhi so that it doesn't attempt to insert instructions that the PHI might reach. This fixes PR21377. llvm-svn: 221187
* [ARM, inline-asm] Fix ARMTargetLowering::getRegForInlineAsmConstraint to returnAkira Hatanaka2014-11-031-1/+12
| | | | | | | | | | | | register class tGPRRegClass if the target is thumb1. This commit fixes a crash that occurs during register allocation which was triggered when a virtual register defined by an inline-asm instruction had to be spilled. rdar://problem/18740489 llvm-svn: 221178
* [X86] 8bit divrem: Improve codegen for AH register extraction.Ahmed Bougacha2014-11-031-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | For 8-bit divrems where the remainder is used, we used to generate: divb %sil shrw $8, %ax movzbl %al, %eax That was to avoid an H-reg access, which is problematic mainly because it isn't possible in REX-prefixed instructions. This patch optimizes that to: divb %sil movzbl %ah, %eax To do that, we explicitly extend AH, and extract the L-subreg in the resulting register. The extension is done using the NOREX variants of MOVZX. To support signed operations, MOVSX_NOREX is also added. Further, this introduces a new SDNode type, [us]divrem_ext_hreg, which is then lowered to a sequence containing a single zext (rather than 2). Differential Revision: http://reviews.llvm.org/D6064 llvm-svn: 221176
* EarlyCSE should ignore calls to @llvm.assumeHal Finkel2014-11-031-0/+36
| | | | | | | | | | | | EarlyCSE uses a simple generation scheme for handling memory-based dependencies, and calls to @llvm.assume (which are marked as writing to memory to ensure the preservation of control dependencies) disturb that scheme unnecessarily. Skipping calls to @llvm.assume is legal, and the alternative (adding AA calls in EarlyCSE) is likely undesirable (we have GVN for that). Fixes PR21448. llvm-svn: 221175
* Reapply: R600: Make sure to inline all internal functionsTom Stellard2014-11-032-1/+25
| | | | | | | | Function calls aren't supported yet. This was reverted due to build breakages, which should be fixed now. llvm-svn: 221173
* [Reassociate] Canonicalize negative constants out of expressions.Chad Rosier2014-11-033-70/+236
| | | | | | | | | This gives CSE/GVN more options to eliminate duplicate expressions. This is a follow up patch to http://reviews.llvm.org/D4904. http://reviews.llvm.org/D5363 llvm-svn: 221171
* Normally an 'optnone' function goes through fast-isel, which does notPaul Robinson2014-11-032-0/+170
| | | | | | | | | | | | call DAGCombiner. But we ran into a case (on Windows) where the calling convention causes argument lowering to bail out of fast-isel, and we end up in CodeGenAndEmitDAG() which does run DAGCombiner. So, we need to make DAGCombiner check for 'optnone' after all. Commit includes the test that found this, plus another one that got missed in the original optnone work. llvm-svn: 221168
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-035-24/+6
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* [AArch64] Fix miscompile of comparison with 0xffffffffffffffffOliver Stannard2014-11-031-0/+36
| | | | | | | Some literals in the AArch64 backend had 15 'f's rather than 16, causing comparisons with a constant 0xffffffffffffffff to be miscompiled. llvm-svn: 221157
* Handle ctor/init_array initialization.Sid Manning2014-11-031-0/+14
| | | | | | | | | Hexagon was not calling InitializeELF and could not select between ctors and init_array. Phabricator revision: http://reviews.llvm.org/D6061 llvm-svn: 221156
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