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* [X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directly, lower from ↵Simon Pilgrim2016-09-141-32/+60
| | | | | | | | generic shuffle Shuffle lowering will correctly lower to MOVSS/MOVSD/PBLEND, improving commutation opportunities llvm-svn: 281471
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-09-147-93/+21
| | | | | | This reverts commit r281323. It caused chromium test failures and a selfhost failure. llvm-svn: 281451
* GlobalISel: mark pointer stores as legal on AArch64.Tim Northover2016-09-141-0/+7
| | | | llvm-svn: 281448
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-25/+5
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* AVX-512: Fixed a bug in kortest.z intrinsicElena Demikhovsky2016-09-141-3/+1
| | | | | | Lowering was wrong - X86ISD::SETCC node should return i8 type. llvm-svn: 281446
* [AVX512BW] Change truncStore action (v16i16->v16i18). It can be legal only ↵Igor Breger2016-09-141-6/+69
| | | | | | | | with AVX512VL. Differential Revision: http://reviews.llvm.org/D24547 llvm-svn: 281445
* [X86] Remove the VCVTSI2SD32 with rounding intrinsic. It's not used by clang ↵Craig Topper2016-09-141-10/+0
| | | | | | and not needed since 32-bit integer to double is always exact. llvm-svn: 281442
* Create a getelementptr instead of sub expr for ValueOffsetPair if theWei Mi2016-09-141-0/+36
| | | | | | | | | | | | value is a pointer. This patch is to fix PR30213. When expanding an expr based on ValueOffsetPair, if the value is of pointer type, we can only create a getelementptr instead of sub expr. Differential Revision: https://reviews.llvm.org/D24088 llvm-svn: 281439
* [sanitizer-coverage] add yet another flavour of coverage instrumentation: ↵Kostya Serebryany2016-09-141-0/+9
| | | | | | trace-pc-guard. The intent is to eventually replace all of {bool coverage, 8bit-counters, trace-pc} with just this one. LLVM part llvm-svn: 281431
* [ObjCARC] Traverse chain downwards to replace uses of argument passed toAkira Hatanaka2016-09-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ObjC library call with call return. ARC contraction tries to replace uses of an argument passed to an objective-c library call with the call return value. For example, in the following IR, it replaces uses of argument %9 and uses of the values discovered traversing the chain upwards (%7 and %8) with the call return %10, if they are dominated by the call to @objc_autoreleaseReturnValue. This transformation enables code-gen to tail-call the call to @objc_autoreleaseReturnValue, which is necessary to enable auto release return value optimization. %7 = tail call i8* @objc_loadWeakRetained(i8** %6) %8 = bitcast i8* %7 to %0* %9 = bitcast %0* %8 to i8* %10 = tail call i8* @objc_autoreleaseReturnValue(i8* %9) ret %0* %8 Since r276727, llvm started removing redundant bitcasts and as a result started feeding the following IR to ARC contraction: %7 = tail call i8* @objc_loadWeakRetained(i8** %6) %8 = bitcast i8* %7 to %0* %9 = tail call i8* @objc_autoreleaseReturnValue(i8* %7) ret %0* %8 ARC contraction no longer does the optimization described above since it only traverses the chain upwards and fails to recognize that the function return can be replaced by the call return. This commit changes ARC contraction to traverse the chain downwards too and replace uses of bitcasts with the call return. rdar://problem/28011339 Differential Revision: https://reviews.llvm.org/D24523 llvm-svn: 281419
* [llvm-cov] Just emit the version number in the index fileVedant Kumar2016-09-131-6/+6
| | | | | | | Having the version information in every view is distracting, especially if there are several sub-views. llvm-svn: 281414
* [AArch64] Simplify patchpoint/stackmap size test (r281301). NFC.Ahmed Bougacha2016-09-132-42/+0
| | | | llvm-svn: 281407
* [CodeGen] Fix invalid shift in mul expansionPawel Bylica2016-09-132-0/+6659
| | | | | | | | | | | | Summary: When expanding mul in type legalization make sure the type for shift amount can actually fit the value. This fixes PR30354 https://llvm.org/bugs/show_bug.cgi?id=30354. Reviewers: hfinkel, majnemer, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D24478 llvm-svn: 281403
* [DAG] Allow build-to-shuffle combine to combine builds from two wide vectors.Michael Kuperstein2016-09-131-99/+31
| | | | | | | | | | | This allows us to, in some cases, create a vector_shuffle out of a build_vector, when the inputs to the build are extract_elements from two different vectors, at least one of which is wider than the output. (E.g. a <8 x i16> being constructed out of elements from a <16 x i16> and a <8 x i16>). Differential Revision: https://reviews.llvm.org/D24491 llvm-svn: 281402
* Next set of additional error checks for invalid Mach-O files for bad load ↵Kevin Enderby2016-09-1314-0/+38
| | | | | | | | | | | | | commands that use the Mach::dyld_info_command type for the load commands that are currently use in the MachOObjectFile constructor. This contains the missing checks for LC_DYLD_INFO and LC_DYLD_INFO_ONLY load commands and the fields for the Mach::dyld_info_command type. llvm-svn: 281400
* [Hexagon] Better handling of HVX vector loweringKrzysztof Parzyszek2016-09-131-0/+21
| | | | | | | - Expand SELECT_CC and BR_CC for vector types. - Implement TLI::isShuffleMaskLegal. llvm-svn: 281397
* add tests for PR28672Sanjay Patel2016-09-131-0/+30
| | | | | | | I'm not sure if we actually want to transform all of these in InstCombine yet, so I'm not labeling these with FIXME. llvm-svn: 281386
* Reapply "InstCombine: Reduce trunc (shl x, K) width."Matt Arsenault2016-09-133-24/+247
| | | | | | | This reapplies r272987 with a fix for infinitely looping when the truncated value is another shift of a constant. llvm-svn: 281379
* AArch64: Cleanup tailcall CC check, enable swiftcc.Matthias Braun2016-09-131-0/+9
| | | | | | | | | | | | | Cleanup/change the code that checks for possible tailcall conventions to look the same as the one in the X86 target. This makes the distinction between calling conventions that can guarnatee tailcalls and the ones that may tailcall more obvious. - Add Swift to the mayTailCall list - PreserveMost seemed to be incorrectly part of the guarnteed tail call list, move it to the mayTailCall list. llvm-svn: 281376
* AMDGPU: Support commuting a FrameIndex operandMatt Arsenault2016-09-131-0/+15
| | | | llvm-svn: 281369
* [LTO] Don't pass SF_Undefined symbols to the IRmover.Davide Italiano2016-09-131-0/+18
| | | | | | This should fix PR 30363. llvm-svn: 281366
* [DAGCombiner] Use APInt directly in (shl (zext (srl x, C)), C) combine range ↵Simon Pilgrim2016-09-131-0/+7
| | | | | | | | | | test To avoid assertion, we must ensure that the inner shift constant is within range before calling ConstantSDNode::getZExtValue(). We already know that the outer shift constant is in range. Followup to D23007 llvm-svn: 281362
* Revert r281336 (and r281337), it caused PR30372.Nico Weber2016-09-133-223/+471
| | | | llvm-svn: 281361
* [Myriad]: set LeonCASA processor featureDouglas Katzman2016-09-131-0/+1
| | | | llvm-svn: 281359
* [X86][SSE] Added AVX512F and additional vector truncate test casesSimon Pilgrim2016-09-131-88/+273
| | | | | | trunc16i16_16i8 is currently commented out due to PR25684 llvm-svn: 281356
* [DAGCombiner] Use APInt directly in (shl (ext (shl x, c1)), c2) combineSimon Pilgrim2016-09-131-0/+18
| | | | | | | | Fix failure to detect out of range shift constants leading to assert in ConstantSDNode::getZExtValue() Followup to D23007 llvm-svn: 281354
* [ConstantFold] Improve the bitcast folding logic for constant vectors.Andrea Di Biagio2016-09-132-23/+22
| | | | | | | | | | | | | | | | | | | | The constant folder didn't know how to always fold bitcasts of constant integer vectors. In particular, it was unable to handle the case where a constant vector had some undef elements, and the resulting (i.e. bitcasted) vector type had more elements than the original vector type. Example: %cast = bitcast <2 x i64><i64 undef, i64 2> to <4 x i32> On a little endian target, %cast could have been folded to: <4 x i32><i32 undef, i32 undef, i32 2, i32 0> This patch improves the folding logic by teaching how to correctly propagate undef elements in the folded vector. Differential Revision: https://reviews.llvm.org/D24301 llvm-svn: 281343
* [X86] Regenerated shift combine tests.Simon Pilgrim2016-09-131-26/+104
| | | | | | Added x86_64 tests llvm-svn: 281341
* [Hexagon] Clear the flow queue after visiting a single instructionKrzysztof Parzyszek2016-09-131-0/+47
| | | | llvm-svn: 281339
* Defer asm errors to post-statement failureNirav Dave2016-09-133-471/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing AsmParser Initialization. Allow errors to be deferred and emitted as part of clean up to simplify and shorten Assembly parser code. This will allow error messages to be emitted in helper functions and be modified by the caller which has better context. As part of this many minor cleanups to the Parser: * Unify parser cleanup on error * Add Workaround for incorrect return values in ParseDirective instances * Tighten checks on error-signifying return values for parser functions and fix in-tree TargetParsers to be more consistent with the changes. * Fix AArch64 test cases checking for spurious error messages that are now fixed. These changes should be backwards compatible with current Target Parsers so long as the error status are correctly returned in appropriate functions. Reviewers: rnk, majnemer Subscribers: aemerson, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D24047 llvm-svn: 281336
* [InstSimplify] Add tests to show missed bitcast folding opportunities.Andrea Di Biagio2016-09-131-0/+144
| | | | | | | | | | InstSimplify doesn't always know how to fold a bitcast of a constant vector. In particular, the logic in InstSimplify doesn't know how to handle the case where the constant vector in input contains some undef elements, and the number of elements is smaller than the number of elements of the bitcast vector type. llvm-svn: 281332
* Revert "[ARM] Promote small global constants to constant pools"James Molloy2016-09-131-109/+0
| | | | | | This reverts commit r281314. Speculatively revert as it's possible this caused linker errors: http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/19656 llvm-svn: 281327
* Remove InstCombine test fileSam Parker2016-09-131-17/+0
| | | | | | My previous commit should of removed a test file but I missed it. llvm-svn: 281326
* [ARM] Add ".code 32" to functions in the ARM instruction setPablo Barrio2016-09-132-2/+26
| | | | | | | | | | | | | | | | | | | Before, only Thumb functions were marked as ".code 16". These ".code x" directives are effective until the next directive of its kind is encountered. Therefore, in code with interleaved ARM and Thumb functions, it was possible to declare a function as ARM and end up with a Thumb function after assembly. A test has been added. An existing test has also been fixed to take this change into account. Reviewers: aschwaighofer, t.p.northover, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D24337 llvm-svn: 281324
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-09-137-21/+93
| | | | | | | | | | | | | For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)). 1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS. 2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS. 3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS). 4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask. 1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win. llvm-svn: 281323
* Enable simplify libcalls for ARM PCSSam Parker2016-09-132-0/+229
| | | | | | | | | | Teach SimplifyLibcalls that in can treat functions annotated with apcs, aapcs or aapcs_vfp like normal C functions if they only take and return integer or pointer values, and the target is not iOS. Differential Revision: https://reviews.llvm.org/D24453 llvm-svn: 281322
* [llvm-cov] - Included footer "Generated by llvm-cov -- llvm version <version ↵Ying Yi2016-09-131-7/+11
| | | | | | | | | | number>" in the coverage report. The llvm-cov version information will be useful to the user when comparing the code coverage across different versions of llvm-cov. This patch provides the llvm-cov version information in the generated coverage report. Differential Revision: https://reviews.llvm.org/D24457 llvm-svn: 281321
* [ARM] Support ldr.w in pseudo instruction ldr rd,=immediatePeter Smith2016-09-131-0/+71
| | | | | | | | | | | | The changes made in r269352, r269353 and r269354 to support the transformation of the ldr rd,=immediate to mov introduced a regression from 3.8 (ldr.w rd, =immediate) not supported. This change puts support back in for ldr.w by means of a t2InstAlias for the .w form. The .w is ignored in ARM state and propagated to the ldr in Thumb2. llvm-svn: 281319
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-131-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). llvm-svn: 281314
* [WebAssembly] Trying to fix broken tests in CodeGen/WebAssembly caused by ↵Eric Liu2016-09-132-2/+2
| | | | | | | | | | | | r281285. Reviewers: bkramer, ddcc, dschuff, sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: https://reviews.llvm.org/D24497 llvm-svn: 281312
* Remove MVT:i1 xor instruction before SELECT. (Performance improvement).Ayman Musa2016-09-132-11/+53
| | | | | | Differential Revision: https://reviews.llvm.org/D23764 llvm-svn: 281308
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-5/+25
| | | | | | | hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-25/+5
| | | | | | | | | | | descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
* AVX-512: Fix for PR28175 - Scalar code optimization.Elena Demikhovsky2016-09-134-22/+88
| | | | | | | | | Optimized (truncate (assertzext x) to i1) and anyext i1 to i8/16/32. Optimization of this patterns is a one more step towards i1 optimization on AVX-512. Differential Revision: https://reviews.llvm.org/D24456 llvm-svn: 281302
* [AArch64] Support stackmap/patchpoint in getInstSizeInBytesDiana Picus2016-09-132-0/+170
| | | | | | | | | | | | | | | | | We currently return 4 for stackmaps and patchpoints, which is very optimistic and can in rare cases cause the branch relaxation pass to fail to relax certain branches. This patch causes getInstSizeInBytes to return a pessimistic estimate of the size as the number of bytes requested in the stackmap/patchpoint. In the future, we could provide a more accurate estimate by sharing some of the logic in AArch64::LowerSTACKMAP/PATCHPOINT. Fixes part of https://llvm.org/bugs/show_bug.cgi?id=28750 Differential Revision: https://reviews.llvm.org/D24073 llvm-svn: 281301
* [X86] Remove masked shufpd/shufps intrinsics and autoupgrade to native ↵Craig Topper2016-09-134-118/+118
| | | | | | vector shuffles. They were removed from clang previously but accidentally left in the backend. llvm-svn: 281300
* DebugInfo: New metadata representation for global variables.Peter Collingbourne2016-09-13136-476/+566
| | | | | | | | | | | | | This patch reverses the edge from DIGlobalVariable to GlobalVariable. This will allow us to more easily preserve debug info metadata when manipulating global variables. Fixes PR30362. A program for upgrading test cases is attached to that bug. Differential Revision: http://reviews.llvm.org/D20147 llvm-svn: 281284
* X86: Conditional tail calls should not have isBarrier = 1Hans Wennborg2016-09-132-3/+31
| | | | | | | | | | That confuses e.g. machine basic block placement, which then doesn't realize that control can fall through a block that ends with a conditional tail call. Instead, isBranch=1 should be set. Also, mark EFLAGS as used by these instructions. llvm-svn: 281281
* Temporarily Revert "[MC] Defer asm errors to post-statement failure" as it's ↵Eric Christopher2016-09-133-223/+471
| | | | | | | | causing errors on the sanitizer bots. This reverts commit r281249. llvm-svn: 281280
* add more tests for PR30273Sanjay Patel2016-09-121-2/+32
| | | | llvm-svn: 281270
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